Shared Memory Video Scaler Architecture for Bandwidth Optimization
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Solution Overview
Problem
Traditional dual video processing chips struggle to produce high-quality video images for multiple channels due to high memory access bandwidth requirements, which limits their ability to handle increased demand for displaying two channels with high video quality, especially with the advent of wider aspect ratios like 16:9.
Innovation Solution
The implementation of systems and methods that reduce memory access bandwidth by allowing multiple video signals to share memory access and using scalers to optimize data storage and processing, including time multiplexing and shared field line buffers, to distribute bandwidth efficiently across video pipeline stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional dual video processing chips are used to process multiple video channels, then video processing capability is provided, but memory access bandwidth requirements become excessively high, limiting the ability to produce high-quality video images for multiple channels
Solution Approach 1:
The patent segments the video processing pipeline into multiple stages (e.g., field line buffering, scaling, noise reduction, de-interlacing) that can operate independently and share memory resources. By dividing the processing tasks across multiple channels and stages, the memory bandwidth requirement per channel is reduced while maintaining overall processing capability.
Solution Approach 2:
The patent merges memory resources to be shared across multiple video channels instead of allocating dedicated memory to each channel. Multiple video channels share common field line buffers and memory structures, reducing total memory bandwidth requirements while enabling high-quality processing of multiple channels simultaneously.
2Manufacturing precision
If 3-D video processing operations (de-interlacing, noise reduction) are implemented on multiple video channels, then video quality is improved, but memory intensive operations increase proportionally with the number of channels
Solution Approach 1:
The patent implements universal field line buffers and memory structures that serve multiple video channels simultaneously. The same memory resources are used by multiple channels for 3-D processing operations, making the memory system multi-functional and reducing the total memory bandwidth required compared to dedicated memory per channel.
Solution Approach 2:
The patent employs periodic memory access patterns where memory resources are allocated to different channels in alternating time slots or fields. This periodic sharing of memory bandwidth allows multiple channels to perform 3-D processing operations without requiring simultaneous full-bandwidth access, reducing peak memory requirements while maintaining video quality.
Data Source
AI summary
A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.