Shared Memory Architecture for Vital and Non-Vital Processor Isolation
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Solution Overview
Problem
In vital railroad control systems, it is challenging to maintain complete autonomy between vital and non-vital functions running on a single processor, preventing non-vital functions from affecting vital operations through inadvertent code execution or excessive system loading, while also ensuring that no single vital processor can transmit complete valid vital data without agreement from all processors.
Innovation Solution
A programmable logic apparatus with a shared memory system, where a first vital processor is interfaced with one port, a non-vital communications processor is separated and interfaced with a second port, and an external second vital processor is interfaced with a third port, allowing for independent data composition and transmission only if all vital processors agree, using a suitable interface for communication between the processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate discrete processors are used for vital and non-vital functions, then independence and safety are improved, but cost and device size increase
Solution Approach 1:
The patent divides the processor into distinct functional segments: a first processor dedicated to vital functions and a second processor dedicated to non-vital functions. Each processor operates independently with its own execution environment, preventing non-vital code from affecting vital operations. This segmentation maintains safety while allowing both functions to coexist in a single integrated device rather than requiring completely separate physical processors.
Solution Approach 2:
The patent implements a unified processor device that performs multiple functions through its dual-processor architecture. The single integrated device handles both vital railroad control operations and non-vital communications/data processing functions, reducing the need for completely separate discrete processors and supporting circuitry while maintaining functional independence.
2Reliability
If multiple vital processors are used for data composition, then data integrity and safety are improved, but communication complexity and transmission coordination increase
Solution Approach 1:
The patent introduces a communication interface that acts as an intermediary between the first processor (vital functions) and the second processor (non-vital functions). This intermediary manages data exchange, allows the second processor to read vital data composition status and write non-vital data, and coordinates transmission authorization without creating complex direct communication pathways between multiple vital processors.
Solution Approach 2:
The patent implements feedback mechanisms where the second processor can read the status of vital data composition from the first processor through the communication interface. This feedback allows the system to monitor data composition progress and coordinate transmission authorization based on the agreement status of all vital processors, ensuring data integrity while managing communication complexity.
Data Source
AI summary
A programmable logic apparatus includes a shared memory having a first port, a second port and a third port; a first vital processor interfaced to the first port of the shared memory; and a non-vital communications processor separated from the first vital processor in the programmable logic apparatus and interfaced to the second port of the shared memory. The third port of the shared memory is an external port structured to interface an external second vital processor.