Shared Mesh Interconnect for Multi-Core Scalability
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Solution Overview
Problem
Current multi-core processor interconnects face challenges in scalability and cost efficiency due to the complexity and power consumption of fully connected mesh networks, which are not adequately addressed by existing mesh interconnect designs, particularly in microserver applications.
Innovation Solution
A shared mesh interconnect fabric is introduced, where a mesh station is shared by multiple core components, utilizing a second intra-die interface to reduce the number of mesh stops and optimize floorplan flexibility, power consumption, and die area, while maintaining coherent interconnect functionality through a logic unit that manages cache and memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fully connected mesh network is used to interconnect cores on a chip, then security and reliability are improved, but the number of connections and manufacturing cost increase rapidly
Solution Approach 1:
The patent segments the fully connected mesh network into multiple virtual channels and logical sub-networks. Each physical connection is divided into multiple virtual channels that can independently transmit different types of traffic (cache coherence, memory access, I/O operations), reducing the need for additional physical connections while maintaining comprehensive connectivity and reliability.
Solution Approach 2:
The patent implements multi-functional mesh stations that can handle multiple types of operations through a single physical connection interface. Each mesh station can simultaneously or alternatively serve as a router, cache controller, and memory interface, allowing the same hardware infrastructure to support diverse communication needs without requiring separate dedicated connections for each function.
2Productivity
If the number of cores on a single chip is increased, then computing throughput is improved, but the complexity of the interconnect fabric increases
Solution Approach 1:
The patent introduces virtual channel dimensions to the physical mesh network. Instead of adding more physical connections to handle increased core count, the system creates multiple logical layers (virtual channels) over the existing physical infrastructure. This dimensional transformation allows O(N²) physical connections to support O(N) or even O(N log N) cores by utilizing parallel virtual channels for traffic aggregation and routing.
Solution Approach 2:
The patent introduces virtual channel multiplexers and intelligent mesh stations as intermediary components between cores and the physical interconnect. These intermediaries aggregate traffic from multiple cores, perform routing decisions, and manage resource allocation, thereby decoupling the linear scaling of core count from the quadratic scaling of connection complexity.
3Power
If high bandwidth mesh interconnects are implemented, then data transmission capability is improved, but power consumption and chip area increase
Solution Approach 1:
The patent implements periodic credit-based flow control mechanisms where mesh stations and cores exchange permission credits in rhythmic intervals. This periodic action allows bandwidth to be allocated in time-sliced fashion to different virtual channels and traffic types, ensuring high overall utilization while preventing any single channel from monopolizing resources and causing excessive power consumption during idle periods.
Solution Approach 2:
The patent dynamically adjusts operational parameters of the mesh interconnect based on traffic demands. Virtual channel priorities, bandwidth allocations, and routing policies are modified in real-time according to workload characteristics, allowing the system to achieve high bandwidth when needed while entering low-power states during idle or low-demand periods, thus decoupling peak bandwidth capability from continuous power consumption.
Data Source
AI summary
A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.