Shared-Electrode MIM Capacitors for Compact BEOL Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in compacting back-end-of-line (BEOL) structures due to the need for multiple through-vias in parallel plate capacitors, which hinders further scaling and integration in semiconductor manufacturing.
Innovation Solution
The implementation of dual Metal-Insulator-Metal (MIM) capacitors that share through-vias, allowing for closer proximity and compaction by forming a shared top electrode and direct contact with bottom metal lines, reducing the number of required through-vias and facilitating more compact BEOL designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional parallel plate capacitors are used in BEOL structures, then electrical connectivity is maintained, but the number of through-vias increases and area occupancy increases, hindering further scaling and integration
Solution Approach 1:
The patent merges multiple capacitor structures by sharing common through-vias and electrode patterns. Specifically, multiple capacitors share common top and bottom electrodes, as well as common through-vias for electrical connectivity, thereby reducing the total number of through-vias required in the BEOL structure while maintaining the necessary capacitance values and electrical connections.
Solution Approach 2:
The shared through-vias and electrode patterns serve multiple functions simultaneously - they provide electrical connectivity for multiple capacitors, act as common reference potentials, and reduce the overall via count. This multi-functionality allows the same structural elements to serve multiple purposes, improving productivity without compromising electrical performance.
2Productivity
If traditional parallel plate capacitors are used in BEOL structures, then electrical connectivity is maintained, but area occupancy increases, hindering further scaling
Solution Approach 1:
The patent combines multiple capacitor structures into a shared footprint by using common top and bottom electrodes that extend across multiple capacitor regions. This merging approach allows multiple capacitors to occupy overlapping or adjacent areas more efficiently, reducing the total area occupancy in the BEOL structure while maintaining individual capacitor functionality.
Solution Approach 2:
The patent utilizes vertical stacking and overlapping electrode patterns in the third dimension to reduce planar area occupancy. By extending electrodes vertically and using shared via structures that penetrate multiple dielectric layers, the design achieves higher capacitance density without proportionally increasing the footprint area, thereby improving scaling efficiency.
Data Source
AI summary
Capacitors and interconnect structures that couple transistors to one another include parallel stacked metal lines separated by dielectric layers. When capacitors and interconnect structures are combined, each top metal capacitor plate can be coupled to the nearest upper metal line by a through-via, while each bottom metal capacitor plate can be coupled directly to the nearest lower metal line without a via. When a back end of line (BEOL) cell includes multiple capacitors, and design rules require shrinking the cell dimensions, substituting an alternative design that has fewer through-vias can facilitate compaction of the BEOL cell. Similarly, placing capacitors in close proximity so that they can share through-vias can allow even further compaction.