Shared MIMO-Viterbi Decoder Logic for Lower Chip Area
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Solution Overview
Problem
Conventional MIMO OFDM receiver systems face complexity and cost challenges due to the need for multiple decoding functions, which complicate circuit design and increase power consumption, especially in high-data-rate wireless communications.
Innovation Solution
The implementation of shared logic circuitry capable of performing both maximum-likelihood (ML) MIMO decoding and Viterbi decoding, allowing these functions to alternate temporally and share resources, reducing the need for separate and extensive circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate decoding circuitry is provided for both MIMO decoding and Viterbi decoding, then decoding functionality and reliability are improved, but device complexity and chip area increase
Solution Approach 1:
The patent implements a universal decoder that can perform both MIMO maximum-likelihood decoding and Viterbi decoding functions. The decoder is configured to selectively execute different decoding algorithms based on the type of data being processed, allowing a single circuit to replace what would traditionally require separate dedicated circuits for each decoding function, thereby reducing device complexity while maintaining full decoding functionality
Solution Approach 2:
The patent combines the MIMO decoder and Viterbi decoder into a single integrated decoding unit. By merging the functionality of separate decoding circuits into one unified structure, the patent reduces the overall device complexity and chip area while ensuring that both decoding functions are available when needed
2Reliability
If separate decoding circuitry is provided for both MIMO decoding and Viterbi decoding, then decoding reliability is improved, but integrated circuit chip area increases
Solution Approach 1:
The universal decoder is designed to perform multiple decoding functions (MIMO and Viterbi) within a single circuit structure, eliminating the need for separate dedicated circuits for each function. This multi-functionality significantly reduces the chip area required while maintaining the reliability benefits of having both decoding capabilities
Solution Approach 2:
By merging the MIMO decoder and Viterbi decoder into one integrated unit, the patent consolidates the chip area required for decoding operations. The unified decoder structure shares common resources and logic, resulting in reduced overall chip area compared to having separate independent decoding circuits
3Reliability
If separate decoding circuitry is provided for both MIMO decoding and Viterbi decoding, then decoding functionality is improved, but power dissipation increases
Solution Approach 1:
The universal decoder performs both MIMO and Viterbi decoding functions within a single power-consuming unit, eliminating the need for two separate powered circuits. By consolidating decoding operations into one multi-functional unit, the patent reduces total power dissipation while maintaining full decoding functionality for different data types
4Reliability
If multiple decoding functions are implemented, then data communication reliability is improved, but ease of manufacture decreases
Solution Approach 1:
The patent implements a universal decoder that handles both MIMO and Viterbi decoding in a single standardized circuit design. This approach simplifies manufacturing compared to producing separate specialized circuits, as it requires only one type of decoder module to be manufactured and integrated, while still providing the reliability benefits of multiple decoding functions
Data Source
AI summary
A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions.


