Shared MMU Address Translation for Accelerator Memory Requests
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Solution Overview
Problem
Existing hardware accelerator implementations require separate memory management units or physical addresses for memory access, leading to increased software complexity and overhead, especially for short tasks, and lack efficient fault handling mechanisms for asynchronous operations.
Innovation Solution
Reuse the memory management circuitry of the processing circuitry for address translation of accelerator-triggered memory access requests, allowing hardware accelerators to operate with virtual addresses and simplify configuration, while implementing asynchronous fault reporting and reduced software overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory management units are used for hardware accelerators, then memory access control is improved, but device complexity and software overhead increase
Solution Approach 1:
The patent merges the memory management functionality for hardware accelerators into the existing processor memory management unit (MMU). Instead of implementing separate memory management units for accelerators, the system reuses the processor's MMU to handle address translation for accelerator-initiated memory requests, thereby reducing overall device complexity while maintaining proper memory access control.
Solution Approach 2:
The processor's memory management unit is designed to serve dual purposes: it handles memory management for both the processor and the hardware accelerator. This multi-functional approach allows the same MMU infrastructure to manage virtual-to-physical address translation for accelerator-triggered requests, eliminating the need for dedicated accelerator memory management hardware.
2Loss of time
If physical addresses are used for accelerator memory access, then address translation overhead is reduced, but software complexity increases
Solution Approach 1:
The hardware accelerator is configured to initiate memory requests using virtual addresses, and the system automatically handles the address translation through the shared MMU. This self-service mechanism allows the accelerator to operate with virtual addresses without requiring manual configuration of physical addresses by software, thereby reducing software complexity while maintaining efficient address translation.
3Productivity
If hardware accelerators operate asynchronously, then processing throughput is improved, but fault handling complexity increases
Solution Approach 1:
The patent introduces an intermediary interface layer between the hardware accelerator and the processor that standardizes fault handling. This interface translates asynchronous fault signals from the accelerator into standardized exceptions or interrupts that the processor can handle using existing mechanisms, thereby maintaining high asynchronous throughput while avoiding the complexity of implementing separate fault handling paths.
Data Source
AI summary
An apparatus comprises processing circuitry to execute instructions; memory management circuitry associated with the processing circuitry, to perform address translation in response to memory access instructions executed by the processing circuitry; and accelerator control interface circuitry to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task. In response to an accelerator-triggered memory access request received at the accelerator control interface circuitry from a given hardware accelerator, the memory management circuitry associated with the processing circuitry is configured to translate a virtual address specified by the accelerator-triggered memory access request to a physical address of a memory system location to be accessed in response to the accelerator-triggered memory access request.