Shared MMU Pool for High-Concurrency Address Translation
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Solution Overview
Problem
Current processors face inefficiencies in address translation due to the use of virtual addresses, which require translation into physical addresses, leading to suboptimal memory access performance.
Innovation Solution
Implementing a processor architecture with a shared MMU pool for multiple physical cores, allowing concurrent address translation requests to be handled by multiple MMUs, reducing latency and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one physical core corresponds to one MMU, then the structure is simple and easy to manage, but the address translation efficiency is limited when high translation requirements occur
Solution Approach 1:
The patent segments the MMU functionality into a pool of multiple MMUs that can be dynamically allocated to different physical cores. Instead of a fixed one-to-one mapping, the system divides the address translation workload across multiple MMU instances, allowing any physical core to access any MMU in the pool based on current demand and availability.
Solution Approach 2:
The patent implements a dynamic MMU allocation mechanism where the mapping between physical cores and MMUs is not fixed but can change based on real-time requirements. The system dynamically assigns MMUs to physical cores depending on address translation demand, enabling flexible resource utilization and improving overall translation efficiency.
2Speed
If a single MMU serves a physical core, then the device complexity is low, but the address translation latency increases under high concurrent access requirements
Solution Approach 1:
The patent merges multiple MMUs into a shared pool that serves multiple physical cores concurrently. By combining the capabilities of multiple MMUs into a single accessible resource pool, the system enables parallel address translation operations across different physical cores, thereby reducing translation latency and improving memory access speed.
Solution Approach 2:
The MMU pool creates a universal address translation service that any physical core can access. Each MMU in the pool can serve any physical core, making the system multi-functional and highly adaptable to varying workloads. This universality allows the system to handle concurrent address translation requests from multiple cores efficiently.
3Productivity
If multiple MMUs are pooled together, then the address translation efficiency improves, but the management and allocation complexity increases
Solution Approach 1:
The patent implements a self-service MMU allocation mechanism where the system automatically manages and assigns MMUs to physical cores based on demand. The MMU pool operates autonomously to balance the distribution of translation tasks across available MMUs, reducing the need for manual intervention and simplifying management while maintaining high throughput.
Data Source
AI summary
A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.