Shared Pinned-Layer MTJ Structure for Compact Low-Power MRAM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current magnetoresistive random access memory (MRAM) devices face issues such as high chip area, high cost, high power consumption, and sensitivity to temperature variations, limiting their effectiveness in magnetic field sensor applications.
Innovation Solution
A semiconductor device and method for fabricating a magnetic tunneling junction (MTJ) structure with specific layer configurations, including a pinned layer, barrier layer, free layer, and top electrode layer, surrounded by a spacer, and formed using techniques like ion beam etching and chemical mechanical polishing to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional MRAM devices are used, then data storage capability is achieved, but chip area is large
Solution Approach 1:
The patent implements a shared pinned layer structure where a single pinned layer serves multiple MTJ cells. The pinned layer is positioned beneath the barrier layer and extends under multiple free layers, allowing multiple storage elements to share common magnetic reference structures. This nesting approach reduces the overall chip area while maintaining data storage capability through efficient space utilization.
Solution Approach 2:
The pinned layer structure is designed to serve multiple functions simultaneously - it provides the magnetic reference for multiple MTJ cells, acts as a barrier to magnetic field interference, and enables compact cell layout. This multi-functional design allows the same structural element to contribute to multiple performance objectives, thereby reducing total device area.
2Use of energy by moving object
If conventional MRAM devices are used, then data storage is achieved, but power consumption is high
Solution Approach 1:
The patent utilizes spin-transfer torque (STT) mechanism where the resistance state of the MTJ is changed by applying a current pulse that generates spin polarization. By controlling the current density and pulse duration parameters, the magnetic moment orientation in the free layer can be switched between parallel and antiparallel states relative to the pinned layer, achieving low-power data storage and retrieval operations.
3Measurement precision
If conventional MRAM devices are used, then basic sensing is achieved, but sensitivity is limited
Solution Approach 1:
The patent creates local magnetic field sensitivity by designing the free layer to respond to external magnetic fields while the pinned layer maintains a fixed reference orientation. The barrier layer is positioned to allow magnetic field penetration to the free layer, creating a localized sensing region with enhanced sensitivity to external magnetic field variations while maintaining overall device stability.
4Reliability
If conventional MRAM devices are used, then operation is achieved, but temperature sensitivity is high
Solution Approach 1:
The pinned layer is designed with high coercivity and strong magnetic anisotropy to maintain stable magnetization orientation despite temperature variations. This pre-configured magnetic stability acts as a cushion against thermal fluctuations, ensuring that the reference magnetic field remains consistent across different operating temperatures and preventing erroneous state transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution reduces chip area, lowers power consumption, and enhances sensitivity by optimizing the MTJ structure, addressing the limitations of existing MRAM devices.
Implementation Method 1
Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance.
Implementation Method 2
forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.