Shared Multi-Bank Memory for Packet Switching Blocking

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Solution Overview

Problem

Current shared memory architectures in packet switches are not fast enough to handle high data transfer rates required for modern networks, such as local area networks (LANs) and wide area networks (WANs), and are prone to blocking issues.

Innovation Solution

The method involves storing sequential data units of a data packet in contiguous banks of a shared memory and maintaining a buffer usage count to manage memory efficiently, allowing for multicasting and reducing blocking by optimizing buffer usage and access control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a shared memory architecture is used for packet switching, then memory sharing and port access control are simplified, but the data transfer speed is insufficient to handle high data rates required for modern networks

Engineering Contradiction:
Improvememory sharing and port access controlVSAvoiddata transfer speed
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The shared memory is divided into multiple banks (first bank, second bank, third bank, fourth bank) that can be accessed simultaneously by different ports. This segmentation allows parallel data transfer operations across multiple memory banks, achieving high data rates while maintaining the shared memory architecture's simplicity for port access control.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If a shared memory architecture is used, then port access control is simplified, but blocking occurs when multiple ports attempt to access memory simultaneously

Engineering Contradiction:
Improveport access controlVSAvoidblocking
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The memory is segmented into multiple banks with independent access paths. When multiple ports attempt to access memory simultaneously, they can access different banks without blocking each other, eliminating the blocking problem while maintaining simplified port access control through the shared memory architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a bank dimension to the memory access structure. Instead of a single memory access path, multiple ports can access different banks in parallel, adding a dimensional aspect to memory access that resolves the blocking issue while preserving the ease of control.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If sequential data units are stored in contiguous banks, then buffer memory utilization is enhanced, but memory management complexity increases

Engineering Contradiction:
Improvebuffer memory utilizationVSAvoidmemory management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The system pre-establishes contiguous bank allocation for sequential data units before data transfer operations. This preliminary organization of memory spaces allows for efficient buffer utilization during actual data transfer, reducing the need for complex real-time memory management decisions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8861515B2Method and apparatus for shared multi-bank memory in a packet switching system
Publication Date: 2014.10.14 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8861515B2 patent drawing
  • US8861515B2 patent drawing
  • US8861515B2 patent drawing

AI summary

Generally, a method and apparatus are disclosed that store sequential data units of a data packet received at an input port in contiguous banks of a buffer in a shared memory, thereby obviating any need for storing linkage information between data units. Data packets can extend through multiple buffers (next-buffer linkage information is much more efficient than next-data-unit linkage information). According to another aspect of the invention, buffer memory utilization can be further enhanced by storing multiple packets in a single buffer. For each buffer, a buffer usage count is stored that indicates the sum (over all packets represented in the buffer) of the number of output ports toward which each of the packets is destined.