Shared Multi-Core Timer for Hardware Time Synchronization
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Solution Overview
Problem
Existing IC devices face inefficiencies in synchronizing timing between multiple processor cores, leading to computational burdens and increased power consumption due to complex software-based solutions for inter-core communication.
Innovation Solution
A shared system timer with a first oscillator, counter register, and event registers is implemented, allowing each processor core to read and write to a centralized timing system, reducing the need for conversion and simplifying event triggering, while incorporating security settings and aliasing to manage access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processor core has its own dedicated timing system, then each core can independently track system time, but timing synchronization between cores becomes complex and computationally inefficient
Solution Approach 1:
The patent merges the timing functionality of multiple processor cores into a single shared system timer. Instead of each core maintaining separate timing systems, all cores access a common counter register that is incremented by a single oscillator, eliminating synchronization complexity while maintaining timing reliability across all cores.
Solution Approach 2:
The shared system timer serves all processor cores universally. The single counter register and oscillator provide timing services to multiple cores simultaneously, allowing the same timing infrastructure to support inter-core communication, event triggering, and time-stamping across the entire multi-core system without requiring core-specific timing resources.
2Reliability
If software-based synchronization is used between processor cores, then timing can be coordinated, but computational overhead and power consumption increase
Solution Approach 1:
The patent replaces software-based timing synchronization with a hardware-based shared timer system. The counter register and oscillator provide hardware-level timing services that all processor cores can access directly, eliminating the need for software synchronization protocols and reducing both computational overhead and power consumption associated with software-based timing coordination.
3Ease of operation
If event registers are accessible by all processor cores, then event triggering is simplified, but access control and security management become more complex
Solution Approach 1:
The patent segments access control for event registers by associating each event register with a specific processor core owner. While all cores can read event registers, write access is restricted to the owner core or cores with appropriate security credentials. This segmentation simplifies event triggering for the owner while implementing security through ownership relationships rather than complex permission matrices.
Data Source
AI summary
An integrated-circuit device comprises a plurality of processor cores and a system timer. The system timer includes a first oscillator that outputs a first clock signal at a first frequency, a first counter register incremented by the first clock signal and a plurality of event registers. Each event register triggers an event when a value held therein is determined to be equal to a value held in the first counter register. The first counter register is readable by each of the plurality of processor cores, and each of the processor cores are capable of writing to at least one of the event registers.