Shared Multipoint Reverse Link for Display Bidirectional Communication
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Solution Overview
Problem
Current systems for transmitting reverse data from driver integrated circuits (DICs) to a timing controller in display devices are costly and complex due to the need for additional traces, connectors, and cables, as well as the complexity of aggregating low-speed reverse data, which often results in near-end crosstalk and increased costs.
Innovation Solution
A shared data lane and synchronization lane system where the timing controller sends a synchronization pulse to all DICs, allowing each to transmit reverse data in non-overlapping time slots, with on-chip or on-board terminations to manage impedance and prevent collisions, thereby reducing the need for dedicated reverse lanes and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If individual forward links are used as bi-directional links, then reverse data transmission is enabled, but near end crosstalk occurs and signal quality deteriorates
Solution Approach 1:
The reverse data transmission is segmented into time slots for different DICs, with each DIC transmitting in its designated time slot. This time-division multiplexing approach allows bidirectional communication while preventing simultaneous transmissions that would cause near end crosstalk.
Solution Approach 2:
The system uses periodic synchronization pulses sent from the TCON to each DIC to coordinate transmission timing. Each DIC transmits reverse data periodically in its assigned time slot, ensuring organized communication without interference.
2Reliability
If dedicated reverse lanes are added for each DIC, then reverse data transmission is reliable, but system cost and complexity increase due to additional traces, connectors, and cables
Solution Approach 1:
Multiple reverse data channels from different DICs are merged into a single shared data lane. Each DIC transmits in its own time slot on this shared lane, eliminating the need for separate physical lanes, traces, connectors, and cables for each DIC, thereby reducing system complexity and cost while maintaining reliable transmission.
Solution Approach 2:
The shared data lane serves multiple functions: it carries reverse data from all DICs, uses the same physical infrastructure for all transmissions, and supports both forward and reverse communication directions. This multi-functional approach eliminates the need for dedicated infrastructure per DIC.
3Speed
If a chip is added to aggregate low-speed reverse links, then high-speed transmission to TCON is achieved, but cost and complexity increase
Solution Approach 1:
Each DIC independently manages its own reverse data transmission by buffering data locally and transmitting in its assigned time slot without requiring an external aggregation chip. The DICs self-coordinate through synchronization pulses, eliminating the need for additional aggregation components while achieving efficient high-speed transmission to the TCON.
4Productivity
If multiple DICs transmit simultaneously on shared lanes, then communication efficiency is high, but data collisions occur
Solution Approach 1:
The shared data lane is segmented into distinct time slots for each DIC, allowing multiple DICs to transmit reverse data simultaneously in different time windows. This time-division approach maintains high communication efficiency while preventing data collisions through temporal separation.
Solution Approach 2:
The TCON sends synchronization pulses to each DIC as feedback to coordinate transmission timing. Each DIC uses these synchronization signals to determine when to transmit in its assigned time slot, ensuring orderly communication without collisions while maximizing channel utilization.
Data Source
AI summary
A display interface for transmitting reverse data. The display interface includes a timing controller, a first plurality of driver integrated circuits, a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits, and a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits. Each of the first plurality of driver integrated circuits has a data input configured to receive reverse data from a display panel, and a buffer configured to store reverse data. The timing controller is configured to periodically send a synchronization pulse having a triggering edge. Each of the first plurality of driver integrated circuits is configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.