Shared-Resource Matrix Arithmetic Circuit for Multiple Precision
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Solution Overview
Problem
Existing matrix product operations for floating-point data in high performance computing and machine learning applications require long calculation times, and existing arithmetic circuits for handling multiple precision levels result in increased circuit area and reduced usage efficiency due to support for unused precision levels.
Innovation Solution
A matrix arithmetic circuit with a two-dimensional systolic array configuration that includes high-precision multipliers and low-precision multipliers arranged in a lattice pattern, combined with an auxiliary operator for digit alignment and addition, allowing switching between low-precision and high-precision calculation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing arithmetic circuits support multiple precision levels, then versatility is improved, but circuit area increases and usage efficiency decreases
Solution Approach 1:
The patent implements a unified matrix arithmetic circuit that can operate in both low-precision mode (using the matrix operator directly) and high-precision mode (using the matrix operator combined with auxiliary operators for digit alignment and addition). This multi-functional design allows the same hardware resources to serve multiple precision requirements without requiring separate dedicated circuits for each precision level, thereby improving versatility while avoiding the circuit area expansion that would result from providing separate arithmetic circuits for each precision level.
2Adaptability or versatility
If existing arithmetic circuits support multiple precision levels, then versatility is improved, but usage efficiency decreases
Solution Approach 1:
The patent creates a universal matrix arithmetic circuit that can be dynamically configured for different precision levels through mode selection. The same matrix operator and auxiliary operators serve both low-precision and high-precision operations, ensuring high utilization rates regardless of the precision level required. This eliminates the resource underutilization that occurs when dedicated circuits for unused precision levels are provided, thereby maintaining high usage efficiency while achieving versatility.
Solution Approach 2:
The patent employs dynamic mode switching between low-precision and high-precision operations based on the computational requirements. The circuit can adaptively select the appropriate operation mode, ensuring that resources are optimally utilized for the current task. This dynamic adaptability prevents the efficiency loss associated with static designs that must accommodate all precision levels simultaneously through dedicated hardware.
3Power
If floating-point operations are used for high performance computing and machine learning, then computational capability is improved, but calculation time increases
Solution Approach 1:
The patent segments the matrix product operation into distinct functional components: a matrix operator for core multiplication and auxiliary operators for digit alignment and addition. This segmentation allows the circuit to process floating-point operations in an optimized pipeline manner, where different stages can operate concurrently or be selectively activated based on precision requirements. By dividing the computational task into manageable segments, the circuit achieves high computational capability while reducing the overall calculation time compared to sequential processing approaches.
Data Source
AI summary
A matrix arithmetic circuit performs an operation of a matrix product and includes a plurality of second operators, each of which includes a plurality of first operators and an auxiliary operator coupled to each of the plurality of first operators, arranged in a lattice pattern. In each of the plurality of second operators, each of the plurality of first operators multiplies a submatrix generated by dividing a multiplier of the matrix product by a submatrix generated by dividing a multiplicand to calculate a submatrix product, and the auxiliary operator performs digit alignment and addition of the submatrix product calculated by each of the plurality of first operators.