Shared Netlist Generation for Reconfigurable Circuit Area Reduction
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Solution Overview
Problem
Existing reconfigurable circuit generation methods result in large area and high costs due to high flexibility, and processing time is long as layout and wiring are performed individually for each application, making it difficult to reduce the area of reconfigurable circuits effectively.
Innovation Solution
A reconfigurable circuit generation device and method that generates a shared netlist among multiple netlists with common portions, reducing resources by implementing the shared netlist on a reconfigurable circuit, thereby reducing the area and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If layout and wiring are performed individually for each application netlist, then each application can be implemented correctly, but processing time becomes long and area reduction is difficult
Solution Approach 1:
The patent merges multiple individual layout and wiring processes into a single integrated process. By extracting common portions from multiple application netlists and performing layout and wiring once on the merged netlist, the system eliminates redundant processing while ensuring correct implementation of all applications through the shared common portion.
Solution Approach 2:
The patent creates a universal common portion that serves multiple application netlists simultaneously. This common portion contains layout and wiring information that can be reused across different applications, making the layout and wiring process multi-functional rather than application-specific.
2Reliability
If layout and wiring are performed individually for each application netlist, then each application can be implemented correctly, but area reduction of the reconfigurable circuit becomes difficult
Solution Approach 1:
The patent merges multiple individual layout and wiring processes into a single integrated process. By extracting common portions from multiple application netlists and performing layout and wiring once on the merged netlist, the system eliminates redundant processing while ensuring correct implementation of all applications through the shared common portion.
Solution Approach 2:
The patent creates a universal common portion that serves multiple application netlists simultaneously. This common portion contains layout and wiring information that can be reused across different applications, making the layout and wiring process multi-functional rather than application-specific.
3Adaptability or versatility
If a general purpose reconfigurable circuit is used to achieve high flexibility, then various applications can be implemented, but area becomes large and costs increase
Solution Approach 1:
The patent applies local quality by differentiating between common portions and application-specific portions of netlists. The common portion is processed once with high-quality universal layout and wiring, while application-specific portions are handled individually, allowing the system to achieve adequate flexibility for multiple applications without requiring the full flexibility of a general-purpose reconfigurable circuit.
Solution Approach 2:
The patent creates a universal common portion that serves multiple application netlists simultaneously. This common portion contains layout and wiring information that can be reused across different applications, making the layout and wiring process multi-functional rather than application-specific.
Data Source
AI summary
A reconfigurable circuit generation device comprises: a netlist generation unit that generates as a shared netlist a netlist that can be shared among a plurality of netlists having a common portion, and a resource reduction unit that reduces resources of the reconfigurable circuit where the plurality of netlists are to be implemented, in a range in which the shared netlist can be implemented.


