Shared Neural Memory Mapping for Low-Area Multi-Access Storage
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Solution Overview
Problem
Existing neural network devices face challenges in efficiently managing memory requirements for various applications, leading to irregular floorplans and high area costs due to varying storage needs, which are not optimally addressed by single- or multi-ported SRAMs.
Innovation Solution
A neural network device with a configurable memory mapping unit that assigns physical memory sections dynamically based on application needs, using a combination of memory banks and address ranges, with a memory-interface module to manage access and avoid conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate physical memories are provided for different storage purposes (event queue, state memory, weight memory, connectivity memory), then memory access times are minimized and independent memory accesses can take place, but the device requires a large surface area and results in irregular floorplans with high area costs
Solution Approach 1:
The patent merges multiple separate physical memories into a single shared physical memory space. Different storage purposes (event queue, state memory, weight memory, connectivity memory) are mapped to different address ranges within the same physical memory, eliminating the need for separate memory blocks and reducing silicon footprint while maintaining independent access capability through address space partitioning
Solution Approach 2:
The patent transitions from a spatial dimension approach (separate physical memory blocks) to an address space dimension approach (virtual memory mapping). By using configurable memory mapping that assigns different address ranges to different storage purposes, the system achieves memory isolation without physical separation, thereby reducing area while maintaining performance
2Adaptability or versatility
If multi-ported SRAMs are used to provide various storage spaces, then access conflicts can be managed, but the area-costs per bit are substantially higher than single-ported SRAMs
Solution Approach 1:
Instead of using expensive multi-ported SRAMs, the patent creates virtual copies of memory spaces through address mapping. Different storage purposes are represented as different address ranges in a unified memory space, allowing independent access without requiring physically separate or multi-ported memory structures, thus reducing area cost per bit
3Adaptability or versatility
If large storage space is provided for each purpose to handle arbitrary applications, then adaptability is improved, but the floorplan becomes irregular and inefficient with substantial white space
Solution Approach 1:
The patent implements dynamic memory mapping where address ranges can be configured based on application requirements. The configurable memory mapping allows the system to adapt storage allocation to actual needs, providing large address space for flexibility while efficiently utilizing physical memory resources, thereby reducing wasted area in the floorplan
Data Source
AI summary
A neural network device includes a shared physical memory that has a plurality of independently accessible memory sections. The neural network device further includes a data processor core to execute instructions. The instructions include at least one instruction involving multiple memory access operations specifying respective logical memory addresses in a plurality of logical memories. During configuration of the neural network device for a particular application, respective memory sections of the plurality of independently accessible memory sections are assigned to respective logical memories of the plurality of logical memories. In accordance with the configuration, each logical memory address of the respective logical memory addresses is mapped to a physical address by providing an indication of a memory section of the plurality of independently accessible memory sections and a row address within the memory section.