Shared Neural Network Processing Circuit for Convolution and Pooling
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Solution Overview
Problem
Existing neural network processing methods require large-scale hardware circuits due to the need for separate dedicated circuits for convolution operations and pooling operations, leading to inefficiencies and increased circuit size.
Innovation Solution
A processing apparatus that integrates convolution operations and pooling operations using a shared computation circuit, comprising a multiplier circuit, memory, adding circuit, comparison circuit, and selection circuit, which sets filter weights and performs multiplication, accumulation, and selection operations to efficiently execute both operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate dedicated circuits are used for convolution operations and pooling operations, then the reliability of operation performance is improved, but the device complexity increases
Solution Approach 1:
The patent applies universality by designing a single computation circuit that can perform both convolution operations and pooling operations through configurable parameters. The circuit uses the same multiplier, adder, and memory structures for both operation types, controlled by configuration signals that adjust the behavior of shared components, thereby reducing device complexity while maintaining operational reliability.
Solution Approach 2:
The patent merges the previously separate convolution and pooling circuits into a unified computation circuit. The multiplier circuit, adding circuit, memory, and control logic are combined into a single integrated structure that can be configured to perform either convolution or pooling operations, directly addressing the contradiction by reducing overall circuit size while preserving the functional capabilities of both operation types.
2Manufacturing precision
If separate dedicated circuits are used for convolution operations and pooling operations, then the manufacturing precision of operation-specific hardware is improved, but the device complexity increases
Solution Approach 1:
The computation circuit is designed with universal components that can be configured for different operation types. The same multiplier, adder, and memory structures serve both convolution and pooling functions, reducing the total number of hardware components needed while maintaining the precision required for each specific operation through configurable parameters and control logic.
3Device complexity
If a shared computation circuit is used for convolution and pooling operations, then the device complexity is reduced, but the processing speed may be affected
Solution Approach 1:
The patent applies dynamics by making the computation circuit reconfigurable through configuration signals. The circuit can dynamically switch between convolution and pooling operation modes, adjusting the behavior of shared components based on the required operation type. This dynamic configuration allows the circuit to optimize its performance for each operation mode while maintaining a compact structure.
Solution Approach 2:
The shared computation circuit maintains continuous useful action by efficiently switching between different operation types without requiring separate dedicated hardware. The circuit processes data continuously, adapting its operation mode through configuration signals rather than requiring physical reconfiguration, thereby maintaining processing speed while reducing device complexity.
Data Source
AI summary
A processing apparatus is provided. A multiplier circuit sequentially outputs a multiplication result obtained by multiplying each of a plurality of items of data with a corresponding filter weight. An adding circuit adds the multiplication result output by the multiplier circuit with data held in a memory and outputs an adding result. A comparison circuit compares the multiplication result output by the multiplier circuit with the data held in the memory, and outputs one of the multiplication result output by the multiplier circuit and the data held in the memory. A selection circuit outputs, to the memory, one of the output from the adding circuit and the output from the comparison circuit to be held in the memory.