Shared-Node Clock Gater for Low-Setup-Time Clock Gating
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Solution Overview
Problem
Clock gaters in integrated circuits face challenges in minimizing setup time while maintaining efficient clock signal distribution, often resulting in clock skew issues due to race conditions and increased setup operations.
Innovation Solution
The implementation of a clock gater with dynamic logic gates and a latch that shares nodes, utilizing CMOS circuits with n- and p-type transistors, to manage clock signals by precharging and evaluating stages, ensuring simultaneous receipt of clock and enable signals, thus minimizing setup time and surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock gaters are used with separate logic circuits and latches, then the clock signal can be gated, but the setup time increases and clock skew issues occur due to race conditions
Solution Approach 1:
The patent merges the logic circuit and latch into a single integrated structure where the latch shares first and second nodes with the logic circuit. This integration eliminates the separate connection paths that cause race conditions, allowing the clock signal to pass through both functions simultaneously without timing mismatches, thereby reducing setup time while maintaining reliable clock signal distribution.
2Reliability
If traditional clock gaters with separate logic circuits and latches are implemented, then clock gating functionality is achieved, but the surface area required increases
Solution Approach 1:
By integrating the logic circuit and latch into a unified structure with shared nodes, the patent reduces the total component count and interconnections required. This merging eliminates redundant circuitry and reduces the overall surface area occupied by the clock gater while preserving complete clock gating functionality.
3Ease of operation
If clock gaters use separate logic circuits and latches, then clock signal control is possible, but clock skew issues arise due to race conditions
Solution Approach 1:
The integrated design where the latch shares nodes with the logic circuit ensures that both the enable signal and clock signal are processed simultaneously through the same physical nodes. This eliminates the temporal separation between logic evaluation and latch capture that causes race conditions, thereby preventing clock skew while maintaining ease of clock signal control.
4Reliability
If more setup operations are added to clock gaters, then clock signal distribution can be managed, but the complexity and surface area increase
Solution Approach 1:
The patent achieves reliable clock signal distribution through a single integrated structure that combines logic circuit and latch functions. This merger eliminates the need for multiple separate setup operations that would be required in traditional designs with separate components, thereby reducing device complexity while maintaining distribution reliability.
Data Source
AI summary
A clock gater includes a first circuit configured to receive a clock signal. The first circuit includes a first subcircuit and a second subcircuit. A latch is configured to receive the clock signal. The latch is connected to the first circuit at each of a first node and a second node. The latch includes a third subcircuit and a fourth subcircuit. The first subcircuit and the third subcircuit are configured to pull the first node and the second node, respectively, to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal. The second subcircuit and the fourth subcircuit are configured to pull the first node and the second node, respectively, to complementary voltages in response to a second state of the clock signal in order to pass the clock signal, the second state of the clock signal being different from the first state of the clock signal.