Shared-Node Calibration Circuit for Stable Memory Impedance Matching
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Solution Overview
Problem
Conventional calibration circuits for semiconductor memory devices have separate pull-up and pull-down calibration paths, which are influenced by PVT variations, leading to inaccurate impedance matching and increased PVT sensitivity.
Innovation Solution
A calibration circuit with a common node shared by both pull-up and pull-down calibration paths, utilizing a comparator and digital filters to adjust codes and match the resistance values of internal resistance units to an external resistor, reducing PVT variations and improving impedance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate pull-up and pull-down calibration paths are used, then the calibration circuit can independently adjust each path, but the circuit becomes more sensitive to PVT variations and impedance matching accuracy deteriorates
Solution Approach 1:
The patent merges the pull-up calibration path and pull-down calibration path into a single integrated calibration path that shares common nodes. This integration reduces the number of separate components and nodes, thereby reducing sensitivity to PVT variations while maintaining the ability to independently adjust pull-up and pull-down resistance values through separate control signals, ultimately improving impedance matching accuracy.
2Adaptability or versatility
If separate calibration paths are used, then each path can be optimized independently, but the overall circuit complexity increases
Solution Approach 1:
The patent combines multiple calibration paths into a single integrated path with shared nodes, reducing the overall circuit complexity while maintaining optimization flexibility through separate control signals for pull-up and pull-down resistance adjustment.
Solution Approach 2:
The integrated calibration path serves multiple functions: it can independently adjust pull-up resistance, independently adjust pull-down resistance, and provide a unified reference for impedance matching, thereby reducing circuit complexity while maintaining optimization flexibility.
3Adaptability or versatility
If separate calibration paths are used, then each path can be calibrated independently, but PVT variation influence increases
Solution Approach 1:
By merging the calibration paths and reducing the number of separate nodes, the patent minimizes the components affected by PVT variations while maintaining independent calibration capability through separate control signals, thereby reducing overall PVT sensitivity.
Solution Approach 2:
The patent introduces a unified reference node that acts as an intermediary for both pull-up and pull-down calibration, providing a common reference point that reduces the impact of PVT variations on the overall calibration accuracy while allowing independent adjustment of each path.
Data Source
AI summary
A calibration circuit includes first and second pull-up units each receiving a pull-up code and connected between a pad connected with an external resistor and a first power supply voltage, a pull-down unit connected between the pad and a second power supply voltage and receiving a pull-down code, a comparator comparing a first voltage with a reference voltage and then compare a second voltage with the reference voltage, a first digital filter adjusting the pull-up code based on a first comparison result of the first voltage with the reference voltage, and a second digital filter adjusting the pull-down code based on a second comparison result of the second voltage with the reference voltage.