Shared Non-Pipelined Execution Resources Across Cores
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Solution Overview
Problem
Current processor architectures face challenges in efficiently executing non-pipelined instructions due to their complex nature and high power consumption, leading to performance degradation and increased latency, as they often require serial execution and additional cycles, which can block pipelined instructions and increase heat generation.
Innovation Solution
The solution involves utilizing inactive non-pipelined operation resources in one processing core to execute non-pipelined instructions on behalf of another core within the same processing unit, allowing for concurrent execution without the need for multiple instances of non-pipelined execution logic, thereby reducing power consumption and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-pipelined instructions are executed using dedicated execution logic, then execution accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent makes non-pipelined execution logic accessible to multiple processing cores, allowing a single instance of complex execution logic to serve multiple cores. This multi-functional approach maintains execution accuracy for non-pipelined instructions while reducing the number of duplicate logic instances across the processor.
Solution Approach 2:
The patent combines multiple instances of non-pipelined execution logic into a shared resource that can be accessed by multiple processing cores. By merging duplicate logic instances into a single shared unit, the overall device complexity and power consumption are reduced while maintaining the ability to execute non-pipelined instructions accurately.
2Productivity
If multiple instances of non-pipelined execution logic are implemented, then concurrent execution of non-pipelined instructions is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent introduces an intermediary mechanism (the shared non-pipelined execution logic accessible by multiple cores) that enables concurrent execution without requiring multiple full instances of the execution logic. This intermediary approach allows multiple cores to utilize the same execution resource, achieving concurrent execution capability while avoiding the complexity of duplicating the entire execution logic for each core.
Data Source
AI summary
A method and circuit arrangement utilize inactive non-pipelined operation resources in one processing core of a multi-core processing unit to execute non-pipelined instructions on behalf of another processing core in the same processing unit. Adjacent processing cores in a processing unit may be coupled together such that, for example, when one processing core's non-pipelined execution sequencer is busy, that processing core may issue into another processing core's non-pipelined execution sequencer if that other processing core's non-pipelined execution sequencer is idle, thereby providing intermittent concurrent execution of multiple non-pipelined instructions within each individual processing core.