Shared Nonvolatile Memory for Multi-Processor Initialization
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Solution Overview
Problem
The high cost and complexity of manufacturing mobile devices with multiple processing components, particularly due to the need for multiple nonvolatile memory components for initialization, which also increase power consumption and reduce battery life.
Innovation Solution
A shared nonvolatile memory system where startup logic and configuration data are stored in a single nonvolatile memory and copied to volatile main memory during initialization, allowing each processing component to access it, thereby reducing the necessity for multiple nonvolatile memory components and simplifying design and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processing component has its own dedicated nonvolatile memory, then startup initialization is fast and reliable, but manufacturing cost increases and power consumption increases
Solution Approach 1:
The patent merges multiple dedicated nonvolatile memory components into a single shared nonvolatile memory that serves multiple processing components. The memory controller manages access from multiple sources (first processor, second processor, and I/O bus) to the single memory component, eliminating redundant hardware while maintaining reliable startup initialization for all components.
Solution Approach 2:
The shared nonvolatile memory is designed to serve multiple functions and multiple processing components simultaneously. It can be accessed by the first processor, second processor, and I/O bus for loading startup logic and configuration data, making a single component universal for initialization needs of all components.
2Reliability
If each processing component has its own dedicated nonvolatile memory, then startup initialization is reliable, but device complexity increases
Solution Approach 1:
The patent consolidates multiple separate nonvolatile memory components into one shared memory component with a centralized memory controller. This merging reduces the total number of components and interfaces from multiple dedicated memories to a single shared resource with unified control logic.
Solution Approach 2:
The shared nonvolatile memory system is designed to be universally accessible by multiple processing components and the I/O bus. The memory controller provides universal access mechanisms that allow different sources to load their respective startup logic and configuration data from the same memory component, reducing overall system complexity.
3Speed
If NOR flash memory is used for fast startup, then startup speed is fast, but manufacturing cost increases
Solution Approach 1:
The system performs preliminary action by copying startup logic and configuration data from the shared nonvolatile memory to volatile main memory before the processing components need to execute them. This pre-loading into faster volatile memory ensures fast startup performance while allowing the use of cheaper non-NOR flash memory for permanent storage.
Solution Approach 2:
The volatile main memory acts as an intermediary between the shared nonvolatile memory and the processing components. Data is first loaded from the cost-effective nonvolatile memory into the volatile main memory, which then provides fast access to the processors during startup and operation, decoupling the cost constraint from the speed requirement.
Data Source
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AI summary
A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.