Shared Op-Amp Input Discharge for Pipelined ADC Linearity

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Solution Overview

Problem

Pipelined analog-to-digital converters that share operational amplifiers between stages or channels suffer from the memory effect, leading to non-linearity and increased power consumption, which affects the accuracy and efficiency of the conversion process.

Innovation Solution

The design incorporates a folded cascode operational amplifier with time-multiplexed input circuits that connect to a common mode voltage during sampling operations to discharge parasitic capacitance, reducing residual errors and power consumption without altering the existing timing or requiring additional timing circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If operational amplifiers are shared between pipeline stages to reduce power consumption, then power consumption is reduced, but memory effect occurs causing non-linearity

Engineering Contradiction:
Improvepower consumptionVSAvoidlinearity
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The harmful parasitic capacitance is extracted and discharged through a dedicated discharge path during the sampling phase, separating the harmful charge accumulation from the signal processing function. This allows the operational amplifier to be shared without accumulating memory effects that cause non-linearity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The parasitic capacitance is discharged during the sampling phase before the signal processing phase begins. This preliminary action prevents the accumulation of harmful charges that would otherwise cause memory effects and non-linearity in subsequent operations.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If operational amplifiers are shared between pipeline stages, then the number of operational amplifiers is reduced, but residual errors increase due to memory effect

Engineering Contradiction:
Improvenumber of operational amplifiersVSAvoidconversion accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The harmful parasitic capacitance is extracted and discharged through a dedicated discharge path, removing the source of memory effects and residual errors. This enables accurate shared operation without the degradation caused by charge accumulation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The parasitic capacitance is discharged during the sampling phase before signal processing begins, preventing the accumulation of errors that would affect measurement precision. This preliminary discharge ensures accurate conversion even with shared operational amplifiers.

Inventive Principle:
Principle #10Preliminary action

3Duration of action of moving object

If operational amplifiers remain active during sampling operations, then settling time is maintained, but power consumption increases

Engineering Contradiction:
Improvesettling timeVSAvoidpower consumption
Core Design Contradiction:
Duration of action of moving objectVSLoss of energy

Solution Approach 1:

The operational amplifier is activated periodically only during the signal processing phase and deactivated during the sampling phase. This periodic operation maintains settling time requirements when active while significantly reducing average power consumption through strategic deactivation during sampling.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The operational amplifier serves itself by being deactivated during sampling operations when it is not needed for signal processing. This self-service approach reduces power consumption without compromising performance, as the amplifier is only active when required for its primary function.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7408496B2Method, apparatus and system sharing an operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry
Publication Date: 2008.08.05 MICRON TECHNOLOGY INC
  • US7408496B2 patent drawing
  • US7408496B2 patent drawing
  • US7408496B2 patent drawing

AI summary

A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry. The operational amplifier contains two input circuits that are time multiplexed in a manner that allows capacitance to be discharged at one input circuit while the other input circuit is inputting signals into the amplifier. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.