Shared OP-AMP Input and Output Reset for ADC Memory Effects
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Solution Overview
Problem
Pipelined Algorithmic Analog-to-Digital Converters (ADCs) face the memory effect issue due to residual signals stored in operational amplifier (OP-AMP) capacitances, which affects amplification, especially with large input signals, leading to improper conversion or interference with subsequent pixel conversions in image sensors.
Innovation Solution
An operational amplifier with two pairs of differential inputs and additional reset devices for input and output resetting, utilizing a switched-capacitor network controlled by non-overlapping clocks to reduce memory effects without inserting a separate reset phase, allowing for frequent resets without increasing clock period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge-reset phase is inserted between clock cycles to reduce memory effect, then memory effect is reduced, but clock speed is reduced
Solution Approach 1:
The patent applies preliminary action by performing input reset and output reset operations at the beginning of each phase (phi1 and phi2) before amplification occurs. The input reset switches (113, 114) and output reset switch (116) are activated during the non-overlapping clock phases to clear residual charges from capacitances before the amplification phase begins, preventing memory effect without requiring a separate reset phase between clock cycles.
Solution Approach 2:
The patent implements periodic action through the use of non-overlapping clock phases (phi1 and phi2) that periodically activate reset switches and amplification switches in alternating cycles. This periodic switching allows the same OP-AMP to be shared between multiple stages while maintaining proper reset and amplification timing, enabling frequent resets without increasing the overall clock period.
2Use of energy by moving object
If OP-AMP sharing is implemented to minimize power consumption, then power consumption is reduced, but residual signals from prior phases affect amplification
Solution Approach 1:
The patent applies preliminary action by performing input reset and output reset operations at the beginning of each phase (phi1 and phi2) before amplification occurs. The input reset switches (113, 114) and output reset switch (116) are activated during the non-overlapping clock phases to clear residual charges from capacitances before the amplification phase begins, preventing memory effect without requiring a separate reset phase.
Solution Approach 2:
The patent implements dynamics through time-multiplexed switching that dynamically assigns the OP-AMP to different functions at different times. The switching circuitry (including switches 101-108, 113-116) dynamically connects the OP-AMP to either amplification mode or reset mode based on the current clock phase, allowing a single OP-AMP to serve multiple stages sequentially while maintaining signal integrity through proper timing control.
3Reliability
If reset devices are added to reset inputs and outputs during amplification phases, then memory effect is reduced without increasing clock period, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a single OP-AMP circuit that performs multiple functions: amplification for multiple different stages and reset operations for both input and output. The same OP-AMP (115) is shared between first and second stages, and the same reset infrastructure (switches 113, 114, 116 controlled by phi1 and phi2) serves both input and output reset functions, reducing the need for separate dedicated circuits for each function.
Solution Approach 2:
The patent merges the reset operations for both input and output into the existing amplification phase structure. Instead of adding separate reset phases or independent reset circuits, the patent combines the reset function with the phase-based timing already present in the amplification circuitry, using the same non-overlapping clock phases (phi1, phi2) to coordinate both reset and amplification operations within a unified timing framework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces memory effects and increases the operating clock speed of pipeline ADCs by enabling frequent input and output resets within existing clock cycles, minimizing power consumption and improving conversion accuracy.
Implementation Method 1
residual signals from prior phases, amplification during a phase may be affected by a residue from a prior phase stored in capacitances of the OP-AMP input pair
Implementation Method 2
A first input reset switch device, coupled between signals of the first pair of differential input signals and a reference signal
Data Source
AI summary
An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs.