Shared OTA Pipelined ADC With Flip-Around Sample Hold
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Solution Overview
Problem
Pipelined ADCs face issues with additional noise and power dissipation due to input sample and hold circuitry, which existing technologies attempt to address by eliminating the sample and hold circuit and using a shared operational transconductance amplifier.
Innovation Solution
A 4-phase shared OTA stage is implemented, incorporating a sample and hold circuit, MDAC1, and MDAC2, employing a charge-conserving flip-around architecture to minimize noise and power consumption, with MDAC1 resolving 2 bits plus one bit for error correction and MDAC2 resolving 1 bit plus one bit for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sample and hold circuit is used in pipelined ADC, then the ADC can properly sample and hold analog signals, but it dissipates additional power and injects noise into the ADC
Solution Approach 1:
The patent combines the sample and hold function with the first MDAC stage into a single integrated circuit. The sample and hold capacitors are merged with the MDAC capacitors, eliminating the need for a separate sample and hold circuit. This integration maintains signal sampling accuracy while removing the additional noise and power dissipation that would come from a standalone sample and hold circuit.
Solution Approach 2:
The first MDAC stage is designed to perform multiple functions: it acts as both the multiplying digital-to-analog converter and the sample and hold circuit. By making the first MDAC stage universal, the patent eliminates the need for a dedicated sample and hold circuit, thereby reducing noise and power dissipation while maintaining the necessary signal holding capability during the conversion process.
2Object-generated harmful factors
If the sample and hold circuit is completely eliminated and sampling is done directly onto MDAC capacitors, then noise and power dissipation are reduced, but an independent sampler in parallel with the MDAC is required for the comparators
Solution Approach 1:
The patent merges the sample and hold function into the first MDAC stage, using the same capacitors and circuitry for both purposes. This eliminates the need for an independent parallel sampler while maintaining the necessary sampling and holding functions, thus reducing device complexity compared to having separate circuits for each function.
3Use of energy by stationary object
If a shared OTA is used during different phases by multiple MDACs, then power consumption is reduced, but the settling time and sample rate are limited by the shared amplifier
Solution Approach 1:
The patent implements a dynamic clocking scheme with four distinct phases that actively manages the shared OTA's operation. The clock phases are designed to provide adequate settling time for the shared amplifier while maintaining a high overall sample rate. This dynamic time-division approach allows the shared OTA to serve multiple MDAC stages without becoming a bottleneck, achieving both low power consumption and high productivity.
Data Source
AI summary
A single operational transconductance pipelined ADC incorporating a sample/hold amplifier and multiple MDAC stages. An input signal is sampled on input signal sampling capacitors, and then coupled around an operational transconductance amplifier (OTA) so that the output of the OTA is equal to the sampled voltage. There is no net charge transfer in this operation, so the noise and power dissipation normally associated with an input sample and hold circuitry (SHA) in a pipelined ADC is substantially eliminated. A pipelined ADC using a shared OTA for sample/hold and two MDACs is disclosed.