Shared Packet Memory System for Ethernet Switch Incast Bottlenecks

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Solution Overview

Problem

Ethernet switches face throughput bottlenecks in incast applications due to limited bandwidth utilization and inefficient memory management, particularly in handling simultaneous bursts of packets, which leads to packet drops and wasted bandwidth.

Innovation Solution

Implementing a shared packet memory system with a queueing structure that combines direct communication between input and output ports using a shared memory architecture, where tags are used to manage packet data and metadata, reducing the number of output queue slices and hiding latency through a tag distribution bus and queue cache structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If traditional separate queue structures are used for each output port, then packet management is straightforward, but the number of queues increases significantly and memory efficiency decreases

Engineering Contradiction:
Improvenumber of queuesVSAvoidmemory efficiency
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent combines multiple separate output queues into a single shared queue structure that serves all output ports. Instead of maintaining N separate queues for N output ports, a single shared queue manages packets for all ports, significantly reducing the number of queue structures and improving memory utilization efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared queue structure serves multiple output ports simultaneously, making a single data structure universal for all egress operations. This multi-functional approach allows the same queue to manage packets destined for different output ports, eliminating the need for dedicated queues for each port.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If packets are fetched from switch fabric to egress port, then packet transmission can proceed, but bandwidth is wasted when packets are dropped after fetching

Engineering Contradiction:
Improvepacket transmission rateVSAvoidbandwidth utilization
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The egress pipeline performs preliminary actions by examining packet headers and metadata before packets are fully fetched from the switch fabric. Packets that fail policy checks are identified and dropped in advance, preventing wasted bandwidth from transmitting packets that will ultimately be discarded.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The egress pipeline acts as an intermediary between the switch fabric and the egress port. It inspects packets from the switch fabric, applies policy decisions based on headers and metadata, and only permits compliant packets to reach the egress port, thereby preventing bandwidth waste from transmitting dropped packets.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If more output queue slices are created to handle incast bursts, then packet loss during bursts is reduced, but memory overhead and system complexity increase

Engineering Contradiction:
Improvepacket delivery reliabilityVSAvoidqueue structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shared queue structure dynamically adapts to handle incast bursts by allowing flexible allocation and deallocation of buffer space based on real-time traffic conditions. Instead of static queue slices that increase complexity during bursts, the dynamic shared queue automatically adjusts to accommodate burst traffic while maintaining packet delivery reliability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11700209B2Multi-path packet descriptor delivery scheme
Publication Date: 2023.07.11 INTEL CORP
  • US11700209B2 patent drawing
  • US11700209B2 patent drawing
  • US11700209B2 patent drawing

AI summary

Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.