Shared Conductive Pads for Memory Test Array Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory test arrays face challenges in accommodating more memory elements in limited space and require lengthy testing times, which hinder efficiency and reliability.
Innovation Solution
The implementation of a memory test array design that includes first and second memory arrays with common conductive pads, allowing for shared connections between bit and word lines, and the use of a probe card with multiple rows of parallel probes to transmit electrical signals simultaneously to adjacent memory arrays without overlapping test times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory elements are disposed in the test chip to obtain more memory element data, then the quantity of memory elements increases, but the space occupation increases and the testing time increases
Solution Approach 1:
Adjacent memory arrays share common conductive pads (bit lines or word lines) to reduce redundant test pads. For example, the first memory array and second memory array share common bit lines or common word lines, allowing simultaneous testing of multiple memory arrays with a single probe card configuration, thus increasing memory element quantity without proportionally increasing testing time
Solution Approach 2:
The common conductive pads serve multiple functions by being shared among adjacent memory arrays. The same conductive pads can be used to test different memory arrays by changing the test configuration, making the test chip more versatile and efficient
2Quantity of substance
If more memory elements are disposed in the test chip to obtain more memory element data, then the quantity of memory elements increases, but the space occupation increases
Solution Approach 1:
Adjacent memory arrays share common conductive pads (bit lines or word lines) to reduce redundant test pads. For example, the first memory array and second memory array share common bit lines or common word lines, allowing simultaneous testing of multiple memory arrays with a single probe card configuration, thus increasing memory element quantity without proportionally increasing testing time
Solution Approach 2:
The common conductive pads serve multiple functions by being shared among adjacent memory arrays. The same conductive pads can be used to test different memory arrays by changing the test configuration, making the test chip more versatile and efficient
3Productivity
If traditional separate test pads are used for each memory array, then each memory array can be tested independently, but the testing time is long and the space efficiency is low
Solution Approach 1:
Adjacent memory arrays share common conductive pads (bit lines or word lines) to reduce redundant test pads. For example, the first memory array and second memory array share common bit lines or common word lines, allowing simultaneous testing of multiple memory arrays with a single probe card configuration, thus increasing memory element quantity without proportionally increasing testing time
Data Source
AI summary
A memory test array and a test method thereof are provided. The memory test array includes a first memory array, a second memory array, and a plurality of first common conductive pads. The first memory array includes a plurality of first bit lines and a plurality of first word lines. The second memory array is adjacent to the first memory array and includes a plurality of second bit lines and a plurality of second word lines. Each of the first common conductive pads has a first end and a second end, and the first ends and the second ends are respectively coupled to the first bit lines and the second bit lines, or respectively coupled to the first word lines and the second word lines. The memory test array of the present disclosure can effectively save the area of the memory test chip and make the test process more efficient.