Shared Page Cache Access for Multi-Plane Memory Arrays
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Solution Overview
Problem
In multi-plane memory devices, significant area is consumed by separate page caches and associated bitline path circuitry due to a one-to-one correspondence, leading to unnecessary replication and inefficiency in resource usage, particularly for single bit program operations.
Innovation Solution
Implementing a common page cache circuit shared by multiple memory arrays, with concurrent and time-multiplexed resource access, allowing asynchronous and concurrent operations across the arrays, reducing redundant page cache circuits and optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate page caches and associated bitline path circuitry are implemented for each memory array, then reliability and independent access are improved, but area consumption and device complexity increase significantly
Solution Approach 1:
The patent merges separate page cache circuits into a shared common page cache that serves multiple memory arrays. The page cache is configured to share resources among first and second memory arrays, eliminating the need for duplicate separate caches and reducing overall area consumption while maintaining concurrent access capability.
Solution Approach 2:
The common page cache is designed with multi-functionality to serve multiple memory arrays simultaneously. It can operate in different modes including concurrent access mode where it independently serves both memory arrays, and time-multiplexed mode where it alternates between arrays, providing universal access capability without requiring separate dedicated caches for each array.
2Reliability
If separate page caches are implemented for each memory array, then independent operation and reliability are improved, but resource utilization efficiency deteriorates due to replication
Solution Approach 1:
The patent implements dynamic operation modes for the shared page cache that can adapt to different access patterns. The system can switch between concurrent access mode for independent operations and time-multiplexed mode for resource sharing, optimizing resource utilization efficiency while maintaining reliability through mode-appropriate access control.
3Adaptability or versatility
If separate page cache circuits are replicated for each memory array, then independent access capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines multiple separate page cache circuits into a single shared common page cache that serves multiple memory arrays. This merging reduces device complexity by eliminating redundant circuits while maintaining independent access capability through configurable operation modes that allow concurrent or time-multiplexed access to the shared resource.
4Reliability
If separate page caches are implemented, then access independence is improved, but latency increases due to longer bitline paths
Solution Approach 1:
The patent merges separate page cache circuits into a shared common page cache located closer to the memory arrays, reducing bitline path length. This consolidation eliminates the need for long external bitline paths while maintaining access independence through internal routing and configurable operation modes, thereby reducing access latency.
Data Source
AI summary
A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.