Semiconductor Memory Device Shared Page Data Programming Across Word Lines
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Solution Overview
Problem
Current semiconductor memory devices face limitations in data integration due to the distribution of threshold voltages across memory cells, leading to reduced data storage capacity and increased error rates, particularly in multi-level cell structures like TLC and QLC.
Innovation Solution
The semiconductor memory device employs a method where shared page data is programmed across multiple word lines, utilizing bit-state mapping relations to distribute data efficiently, allowing for increased data storage by combining states and optimizing the distribution of threshold voltages across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in memory cells using conventional single-word-line programming, then the programming process is simple, but the data integration capacity is limited
Solution Approach 1:
The patent segments shared page data into first partial data and second partial data, programming each to different word lines (first word line and second word line respectively). This segmentation allows the memory device to store more data by utilizing multiple word lines simultaneously, thereby increasing data integration capacity while managing programming complexity through systematic data division
Solution Approach 2:
The patent transitions from conventional single-word-line data storage to multi-word-line storage by distributing shared page data across different word lines. This dimensional expansion from one word line to multiple word lines increases the storage capacity and data integration without requiring additional memory cells, effectively utilizing the vertical stacking structure of 3D NAND flash memory
2Reliability
If threshold voltage distribution is narrow in memory cells, then programming is easier, but error rates increase and data integration is limited
Solution Approach 1:
The patent applies different programming approaches to different portions of data based on their characteristics. Shared page data is distributed across multiple word lines with specific bit-state mapping relations, while non-shared data is programmed to individual word lines. This localized quality differentiation optimizes the threshold voltage distribution for each data type, reducing error rates while maximizing data integration capacity
Solution Approach 2:
The patent changes the parameter of threshold voltage distribution by programming data to multiple word lines with different voltage characteristics. By utilizing bit-state mapping relations that combine multiple states, the system expands the effective threshold voltage range, thereby increasing data integration capacity while maintaining reliability through optimized voltage distribution margins
3Quantity of substance
If shared page data is programmed to multiple word lines, then data integration is enhanced, but the programming control complexity increases
Solution Approach 1:
The control logic is designed with multi-functionality to handle both conventional single-word-line programming and the new multi-word-line shared page data programming. The control logic can generate appropriate bit-state mapping relations and manage different programming modes (first program operation and second program operation) within a unified architecture, reducing the need for separate control systems and managing complexity through versatile control mechanisms
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may program shared page data on selected memory cells among the plurality of memory cells. The control logic may control, during the program operation on the selected memory cells, the peripheral circuit to program first partial data of the shared page data to memory cells coupled to a first word line among the selected memory cells, and to program second partial data of the shared page data to memory cells coupled to a second word line different from the first word line among the selected memory cells.