Shared-Parity LDPC Decoding for Large Codeword Processing

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Solution Overview

Problem

Large codewords in data processing systems require significant die area and power, leading to complex data decoding circuits that compromise processing performance when reduced in size.

Innovation Solution

Implementing a data processing system that uses shared parity between sub-codewords, allowing for enhanced error correction power while reducing circuit size and power consumption by aggregating sub-codewords and encoding parity across multiple sub-codewords, enabling time-sharing of data decoding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If large codewords are used to achieve increased data processing performance, then processing performance is improved, but data decoding circuit size and power consumption increase significantly

Engineering Contradiction:
Improvedata processing performanceVSAvoiddata decoding circuit die area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent divides a large codeword into multiple smaller sub-codewords that can be processed independently by separate decoding circuits. This segmentation allows the system to maintain high data processing performance by processing multiple sub-codewords in parallel, while each individual decoding circuit remains compact and power-efficient, avoiding the need for a single large complex decoder.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If data decoding circuit size is reduced to decrease die area and power, then circuit size and power are reduced, but processing performance deteriorates

Engineering Contradiction:
Improvedata decoding circuit die areaVSAvoiddata processing performance
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

The patent combines multiple smaller decoding circuits to process different sub-codewords simultaneously. By merging the outputs of these parallel decoders and reconstituting the complete decoded data, the system achieves high processing performance equivalent to a single large decoder, while each individual circuit remains small and power-efficient.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If large codewords are used to enhance error correction power, then error correction capability is improved, but circuit complexity increases

Engineering Contradiction:
Improveerror correction powerVSAvoiddata decoding circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the error correction function across multiple independent decoding circuits, each handling a sub-codeword. This segmentation maintains strong error correction capability for the overall large codeword while keeping each individual decoder simple and manageable, avoiding the complexity of a single large decoder.

Inventive Principle:
Principle #1Segmentation

4Area of stationary object

If smaller sub-codewords are used to reduce decoding circuit size, then circuit size and power are reduced, but error correction power decreases

Engineering Contradiction:
Improvedata decoding circuit die areaVSAvoiderror correction power
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent combines multiple sub-codewords into a composite structure where error correction capabilities are aggregated. By merging the error correction functions of multiple small decoders working in parallel on different sub-codewords, the system achieves error correction power comparable to a single large decoder, while maintaining small circuit size and low power consumption.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8578241B2Systems and methods for parity sharing data processing
Publication Date: 2013.11.05 GODO KAISHA IP BRIDGE 1
  • US8578241B2 patent drawing
  • US8578241B2 patent drawing
  • US8578241B2 patent drawing

AI summary

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a low density parity check data decoder circuit, and a processing circuit. The processing circuit is operable to: reconstitute a second encoded sub-codeword from a combination of data including the first encoded sub-codeword and the composite sub-codeword; and correct an error in one of the first encoded sub-codeword and the second encoded sub-codeword based at least in part on a combination of the first encoded sub-codeword, the second encoded sub-codeword, and the composite sub-codeword.