Shared Parity Protection for Managed NAND Memory Systems
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Solution Overview
Problem
Managed NAND systems face challenges in implementing Redundant Array of Independent NAND (RAIN) schemes due to limited SRAM resources, leading to performance impacts and overprovisioning issues with generating and storing parity data across different NAND blocks.
Innovation Solution
A parity mapping and management algorithm is introduced to generate shared parity data between cursors, allowing parity data to be overlapped and wrapped in SRAM, with a parity-to-data map updated and flushed to NAND, enabling efficient RAIN scheme operation and reducing the need for extensive SRAM storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity data is generated and stored for each NAND block independently, then data protection reliability is improved, but SRAM resource consumption increases and write performance deteriorates
Solution Approach 1:
The patent merges parity data from multiple different NAND blocks into a single shared SRAM location. Instead of allocating separate SRAM space for each block's parity data, the system combines parity data from multiple blocks and stores it in a shared location, reducing overall SRAM consumption while maintaining protection across all blocks.
Solution Approach 2:
The patent makes SRAM locations universal by allowing them to store parity data for multiple different blocks rather than being dedicated to a single block. A single SRAM location can serve as the parity storage for multiple blocks, increasing resource utilization efficiency and reducing the total SRAM required.
2Reliability
If parity data is stored in SRAM for each NAND block, then data reconstruction capability is improved, but SRAM resource requirements increase
Solution Approach 1:
The patent combines parity data from multiple NAND blocks and stores it in a shared SRAM location, reducing the total quantity of SRAM required while maintaining the ability to reconstruct data for all participating blocks from that single shared location.
Solution Approach 2:
The patent implements a wraparound mechanism where SRAM locations are reused after their parity data has been flushed to NAND. Once parity data is successfully written to NAND storage, the SRAM location becomes available for storing parity data for other blocks, maximizing SRAM utilization and reducing the total SRAM needed.
3Reliability
If extensive SRAM is allocated for parity data storage, then RAIN scheme implementation is improved, but device complexity and overprovisioning increase
Solution Approach 1:
The patent implements a dynamic parity management system where the association between SRAM locations and NAND blocks changes over time. SRAM locations are dynamically assigned to different blocks based on a wraparound scheme, and the system adaptively manages which parity data is active in which SRAM location, reducing the need for large static SRAM allocations.
Solution Approach 2:
The patent employs periodic flushing of parity data from SRAM to NAND storage at defined intervals or triggers. This periodic action allows temporary SRAM resources to be reused for new parity data while ensuring data protection is maintained through periodic persistence to non-volatile storage, reducing the total SRAM required.
Data Source
AI summary
A variety of applications can include apparatus and/or methods that provide shared parity protection to data in memory devices of a memory system. Parity data of different data streams programmed into different blocks of one or more memory devices can be overlapped and wrapped into slots of a volatile memory arranged as a storage device for the parity data. A parity, map of parity-to-data reflecting the overlapping of the parity data can be maintained in the volatile memory along with the overlapped parity. The parity map can be updated as parity data is generated from further programming of the data streams. The parity contents of the volatile memory, including the parity map, can be transferred to a non-volatile memory in response to a determination of an occurrence of a transfer criterion. The parity contents flushed to the non-volatile memory can be used to allow correct data reconstruction in case of failures in programming.