Shared Partial Products in Dot Product Hardware to Cut Latency
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Solution Overview
Problem
Existing hardware implementations of dot product operations face inefficiencies due to high computational complexity and resource requirements, particularly in the generation and addition of partial products, which lead to increased latency and hardware area usage.
Innovation Solution
A hardware module is designed to perform dot product operations by grouping bits of vectors into binary numbers to generate partial products, selecting partial product values based on these binary numbers, and adding them together, reducing the number of partial products and complexity through techniques like recoding and sign manipulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional hardware implementations generate partial products for dot product operations, then the dot product can be computed, but the computational complexity and hardware area requirements increase significantly
Solution Approach 1:
The patent segments the dot product computation into two independent parts: (1) generating partial products by multiplying elements of the first vector with elements of the second vector, and (2) adding these partial products to produce the final result. This segmentation allows each part to be optimized independently, reducing overall complexity while maintaining computational capability.
Solution Approach 2:
The patent introduces a new dimension to the computation by processing vectors of different lengths. Specifically, it handles cases where the first vector has more elements than the second vector by padding the second vector with zeros, effectively transforming the problem into a higher-dimensional space where standard multiplication and addition operations can be applied uniformly.
2Productivity
If traditional hardware implementations generate partial products for dot product operations, then the dot product can be computed, but hardware area requirements increase
Solution Approach 1:
The patent applies partial action by only generating partial products for the minimum number of elements required. When the first vector has more elements than the second vector, it only computes partial products for as many elements as the shorter vector has, effectively performing only the necessary computation and avoiding wasteful hardware resources.
Solution Approach 2:
The patent discards redundant computations by using the length of the shorter vector to determine how many partial products need to be generated. Any potential partial products that would result from multiplying with zero-padded elements are discarded, reducing hardware area requirements while maintaining correct computation results.
3Productivity
If traditional hardware implementations generate partial products for dot product operations, then the dot product can be computed, but latency increases
Solution Approach 1:
The patent performs preliminary action by pre-determining the number of partial products to generate based on the length of the shorter vector. This allows the hardware to be configured in advance with the exact number of computation stages needed, eliminating unnecessary delays and optimizing the computation timeline for minimal latency.
Data Source
AI summary
A hardware module for performing dot product operations includes receiver circuitry receiving a first vector and a second vector, each comprising at least two elements of a binary encoded integer. Logic generates an array of partial products of N rows of bits for a dot product operation between the first vector and the second vector. Grouping circuitry groups bits of the elements of the second vector into a binary number, wherein each binary number is associated with a respective row of the N rows of bits, and selector circuitry selects a partial product value for each of the N rows of bits based on the binary number that is associated with the respective row, such that one partial product is generated per binary number. The hardware module also comprises adder circuitry configured to perform adding the N rows of bits together to compute an output associated with the dot product operation between the first and second vectors.