Shared-Path Frequency Divider for Matched Clock Propagation Delay
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Solution Overview
Problem
Frequency dividers introduce propagation delay mismatch between common and reduced frequency clock signals, leading to operational issues and high power consumption due to the need for additional circuitry and power-intensive delay matching.
Innovation Solution
A frequency divider design that uses shared circuits to provide both common and reduced frequency clock signals with substantially the same propagation delay, eliminating the need for delay matching and reducing power consumption by integrating the enable circuit functionality without additional propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a model delay element is used to match propagation delays in the common frequency clock signal path and reduced frequency clock signal path, then the delay matching accuracy improves, but the device complexity and power consumption increase
Solution Approach 1:
The patent merges the common frequency clock signal path and reduced frequency clock signal path into a single shared propagation path. By using a single path for both clock signals, the propagation delay is inherently matched for both signals, eliminating the need for separate model delay elements and complex delay matching circuitry. This resolves the contradiction by reducing device complexity while maintaining delay matching accuracy through path unification.
Solution Approach 2:
The shared clock signal propagation path serves dual functionality by carrying both the common frequency clock signal and the reduced frequency clock signal. This multi-functional path eliminates the need for separate dedicated paths and delay matching components, thereby reducing device complexity while ensuring consistent propagation delay for both signal types.
2Adaptability or versatility
If a multiplexer is used to select between common frequency clock signal and reduced frequency clock signal, then the adaptability improves, but the propagation delay and power consumption increase
Solution Approach 1:
The patent extracts and removes the multiplexer from the clock signal path by implementing separate generation paths for common frequency and reduced frequency clock signals. Both signals are generated independently and fed directly to the output without requiring multiplexing selection. This eliminates the multiplexer-induced propagation delay while maintaining the ability to provide both frequency options, thus resolving the contradiction between adaptability and time loss.
Solution Approach 2:
The patent segments the clock signal generation into independent parallel paths: one path generates the common frequency clock signal and another path generates the reduced frequency clock signal. Both paths operate independently and feed the output directly, eliminating the need for a multiplexer. This segmentation approach maintains frequency selection adaptability while removing the time penalty associated with multiplexer switching.
3Measurement precision
If additional circuitry is added to match propagation delays, then the delay matching accuracy improves, but the power consumption increases
Solution Approach 1:
The patent merges both clock signal paths into a single shared propagation path, eliminating the need for additional delay matching circuitry. By using one common path for both common frequency and reduced frequency clock signals, the propagation delay is inherently matched without requiring extra components. This resolves the contradiction by reducing power consumption through circuit simplification while maintaining delay matching accuracy.
4Measurement precision
If a frequency divider with two signal propagation paths and model delay element is used, then the delay matching capability improves, but the overall propagation delay and power consumption increase
Solution Approach 1:
The patent merges the two separate signal propagation paths into a single shared path that carries both common frequency and reduced frequency clock signals. This unification eliminates redundant circuitry including model delay elements, thereby improving signal propagation efficiency and reducing overall propagation delay while maintaining the capability to provide both frequency options with matched delays.
Solution Approach 2:
The patent segments the frequency division function into independent parallel generation paths rather than using a single path with delay matching. Each frequency option has its own generation path that feeds directly to the output, eliminating the need for model delay elements and intermediate buffering. This segmentation improves productivity by reducing the total number of gates and propagation stages while maintaining delay matching capability.
Data Source
AI summary
Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.