Shared Phase Alignment Circuitry for Parallel Data Paths
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Solution Overview
Problem
As the number of data paths in a communication system increases, the complexity and cost of aligning the phase of capture clock signals with launch clock signals also increase, due to the need for independent phase alignment processes for each pair of clock signals.
Innovation Solution
The implementation of phase alignment circuitry that adjusts the phases of launch clock signals based on clock slip signals and adjusts the phase of the capture clock signal relative to the launch clock signal using adjustment values specific to each data path, thereby reducing the number of clock signals and simplifying the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If independent phase alignment processes are performed for each capture clock signal and launch clock signal pair, then phase alignment accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges multiple independent phase alignment processes into a single shared phase alignment circuit that serves multiple data paths. Instead of having separate phase alignment circuits for each capture clock/launch clock pair, one phase alignment circuit is shared across multiple data paths, reducing device complexity while maintaining phase alignment functionality through time-multiplexed operation.
Solution Approach 2:
The phase alignment circuit is designed with universal functionality to handle multiple capture clock signals and launch clock signal pairs. The circuit can be configured to work with different clock pairs by receiving control signals that identify which clocks are being aligned, allowing one circuit to perform the function of multiple dedicated circuits.
2Measurement precision
If independent phase alignment processes are performed for each capture clock signal and launch clock signal pair, then phase alignment accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple independent phase alignment processes into a single shared phase alignment circuit that serves multiple data paths. Instead of having separate phase alignment circuits for each capture clock/launch clock pair, one phase alignment circuit is shared across multiple data paths, reducing device complexity while maintaining phase alignment functionality through time-multiplexed operation.
3Productivity
If the number of data paths increases, then data transmission capacity is improved, but the number of clock signals increases, worsening design complexity
Solution Approach 1:
The phase alignment circuit is designed with universal functionality to handle multiple capture clock signals and launch clock signal pairs. The circuit can be configured to work with different clock pairs by receiving control signals that identify which clocks are being aligned, allowing one circuit to perform the function of multiple dedicated circuits.
Solution Approach 2:
The shared phase alignment circuit operates periodically, time-multiplexing its resources across multiple data paths. The circuit sequentially processes different capture clock/launch clock pairs in a periodic manner, allowing each path to receive phase alignment services at regular intervals while sharing the same hardware resources.
Data Source
AI summary
Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.