Shared Physical Layer Logic for Multi-Protocol Interface Management
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Solution Overview
Problem
Conventional communication devices with physical layer hardware are limited to supporting only one protocol stack due to resource management constraints, particularly in power and clock management, which restricts their ability to operate with multiple protocols simultaneously.
Innovation Solution
A common interface logic and hierarchical architecture are implemented to manage clock signaling and power states, allowing multiple port controllers to access and share physical layer resources across different protocols without compromising power and clock management, enabling scalable support for multiple protocols like M-PHY, SSIC, UFS, LLI, and CSI-3.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single protocol stack is supported in the IC, then power and clock management constraints are satisfied, but the number of supported protocols is limited to one
Solution Approach 1:
The system segments protocol support by implementing separate protocol stacks (first protocol stack and second protocol stack) that can independently access the shared PHY through different interface logic paths. This allows multiple protocols to coexist without interfering with each other's resource management, resolving the contradiction between supporting multiple protocols and managing resource complexity.
Solution Approach 2:
The PHY is designed with universal interface logic that can operate with multiple protocol stacks. The shared PHY implements a unified interface framework that accommodates different protocols (such as M-PHY, USB 3.0, PCI Express) through common operational modes, enabling one physical layer to serve multiple protocol functions simultaneously.
2Adaptability or versatility
If multiple protocol stacks are supported simultaneously, then protocol versatility is improved, but power and clock management constraints are violated
Solution Approach 1:
The system implements periodic or selective activation of protocol stacks based on operational needs. The interface logic enables protocols to be activated only when required, allowing the PHY to enter low-power states when certain protocols are inactive. This periodic activation pattern reduces overall power consumption while maintaining support for multiple protocols.
Solution Approach 2:
Different protocol stacks are assigned different power management characteristics and operational modes tailored to their specific requirements. The interface logic provides localized power and clock control for each protocol stack, allowing power-efficient operation by activating only the necessary protocol resources at any given time rather than maintaining all protocols at full power continuously.
3Reliability
If separate PHYs are provided for each protocol, then protocol independence is maintained, but pin and die constraints are exceeded
Solution Approach 1:
Multiple protocol-specific PHY instances are merged into a single shared PHY implementation. The interface logic combines the functional capabilities of what would traditionally require separate PHYs (M-PHY, USB 3.0 PHY, PCI Express PHY) into one unified physical layer block, reducing the total IC area while maintaining protocol independence through logical separation in the interface logic layer.
Solution Approach 2:
The interface logic acts as an intermediary layer between multiple protocol stacks and the shared PHY. This mediator component translates and manages communication between different protocols and the unified PHY, allowing protocol independence to be maintained through software or firmware control rather than requiring separate hardware PHY instances for each protocol.
Data Source
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AI summary
Techniques and mechanisms to provide common interface logic for multiple protocol engines to access physical layer circuitry at different times. In an embodiment, a state machine of an interface device is to participate in exchanges with physical layer resources on behalf of any of various protocol engines coupled to the interface device via different respective interfaces. Based on state transitions by the state machine, circuitry corresponding to a particular one of such interfaces may selectively send a clock signal for operation of a port controller attempting to access the physical layer circuitry. In some embodiments, multiple interface devices are configured to provide an hierarchical interface architecture for more than two port controllers that variously support at least two protocols.