Shared Pick-Up Region Layout for SRAM Well Leakage Control
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Solution Overview
Problem
As integrated circuits (ICs) shrink in size and become more densely packed, leakage current between adjacent n-type and p-type wells increases, leading to higher resistance and deteriorated device performance in SRAM circuits.
Innovation Solution
The placement of shared pick-up regions adjacent to or in contact with n-type and p-type wells, combined with the use of gate-all-around (GAA) or fin field-effect transistors (finFET) in memory cells and peripheral circuits, to reduce leakage current and improve charge distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are made smaller and placed more densely to increase device capacity, then device density increases, but leakage current between adjacent wells increases and device performance deteriorates
Solution Approach 1:
An isolation structure is introduced as an intermediary element between adjacent n-type and p-type wells. This isolation structure prevents direct interaction between the wells, thereby reducing leakage current while allowing the wells to be placed closer together for increased density.
Solution Approach 2:
The isolation structure segments the continuous substrate into distinct regions, electrically separating adjacent wells. This segmentation allows each well to maintain its potential independently, reducing cross-well leakage while enabling closer spacing.
2Area of stationary object
If pick-up regions are placed closer to memory cells to reduce area, then device footprint decreases, but leakage current increases due to proximity between opposite-type wells
Solution Approach 1:
The isolation structure acts as a mediator placed between pick-up regions of opposite types (e.g., between an n-type pick-up region and adjacent p-type structures). This allows pick-up regions to be positioned closer to memory cells for area efficiency while the isolation structure blocks leakage current paths.
Solution Approach 2:
The isolation structure is strategically placed only in specific locations where leakage paths exist between adjacent wells, rather than uniformly across the entire device. This localized approach reduces leakage current while minimizing the impact on device footprint.
Data Source
AI summary
The present disclosure describes a memory structure including a memory cell array. The memory cell array includes memory cells and first n-type wells extending in a first direction. The memory structure also includes a second n-type well formed in a peripheral region of the memory structure. The second n-type well extends in a second direction and is in contact with a first n-type well of the first n-type wells. The memory structure further includes a pick-up region formed in the second n-type well. The pick-up region is electrically coupled to the first n-type well of first n-type wells.