Shared Pillar Memory Cell Structure for 3D NAND Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for improved three-dimensional pillar designs and corresponding fabrication processes for non-volatile memory array technologies, particularly in forming memory cells that minimize unintentional programming of unselected memory cells.
Innovation Solution
A three-dimensional non-volatile memory system utilizing shared pillar structures, where each pillar includes a first end surface contacting one array line from a first set of array lines and a second end surface contacting two array lines from a vertically separated second set of array lines, with each pillar containing a first subset of layers divided for individual storage elements and a second subset of layers shared between storage elements, including a steering element and a state change element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional pillar structures are used with full separation of structures forming each memory cell, then manufacturing precision is improved, but device complexity increases and productivity decreases
Solution Approach 1:
The patent merges the structure forming process by creating a single pillar that contains multiple memory cells. Instead of fabricating separate pillars for each memory cell, the invention forms one pillar structure that houses both first and second memory cells, thereby reducing device complexity while maintaining manufacturing precision through shared fabrication steps.
Solution Approach 2:
The pillar structure is designed to serve multiple functions simultaneously. A single pillar acts as the structural framework for both first and second memory cells, providing mechanical support, electrical isolation, and spatial definition for multiple storage elements within one unified structure.
2Manufacturing precision
If traditional pillar structures with full separation are used, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent merges the structure forming process by creating a single pillar that contains multiple memory cells. Instead of fabricating separate pillars for each memory cell, the invention forms one pillar structure that houses both first and second memory cells, thereby reducing device complexity while maintaining manufacturing precision through shared fabrication steps.
Solution Approach 2:
The pillar structure is formed in advance to contain both memory cells before the individual cell components are assembled. This preliminary formation of the shared pillar structure streamlines the fabrication process by establishing the structural framework early, allowing subsequent steps to focus on filling and configuring the memory cell elements within the pre-formed pillar.
3Device complexity
If rail-stack structures are used, then device complexity is reduced, but unintentional programming of unselected memory cells occurs
Solution Approach 1:
The patent segments the pillar structure into distinct regions for first and second memory cells, with separate steering elements and state change elements for each cell. This segmentation allows independent control and programming of each memory cell within the shared pillar, preventing unintentional programming while maintaining the simplified shared structure.
Solution Approach 2:
The invention applies local quality by providing specific structural features and material compositions tailored to each memory cell's requirements within the shared pillar. Each memory cell has its own steering element and state change element with optimized properties, allowing precise control over programming and reading operations for each cell while sharing common structural elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shared pillar design enhances the precision and efficiency of memory cell formation, reducing unintentional programming of unselected memory cells and improving the overall performance of three-dimensional non-volatile memory arrays.
Implementation Method 1
Materials having a detectable level of change in state, such as a resistance or phase change, are used to form various types of non-volatile semiconductor based memory devices
Implementation Method 2
Diodes or other devices having a non-linear conduction current are typically used as the steering element
Data Source
AI summary
A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.