Shared-Pin Bandwidth Extension Circuit for Parasitic Capacitance
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Solution Overview
Problem
Existing integrated circuit designs face challenges in impedance matching bandwidth due to parasitic capacitance from ESD protection circuits, which limits the bandwidth and affects signal quality.
Innovation Solution
An electronic device with a bandwidth extension circuit and a high-frequency impedance matching circuit, featuring distinct inductors and capacitors to minimize parasitic capacitance and enhance impedance matching, thereby expanding the bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If T-coil circuit with direct node connection is used, then bandwidth extension is attempted, but parasitic capacitance from receiving and transmitting circuits superposes on the nodes, increasing equivalent capacitance and limiting bandwidth
Solution Approach 1:
The patent divides the single T-coil circuit into two separate T-coil circuits, with the first T-coil circuit connected to the receiving circuit and the second T-coil circuit connected to the transmitting circuit. This segmentation prevents the parasitic capacitances from both circuits from superposing on the same node, thereby reducing the total equivalent capacitance and extending the bandwidth.
2Adaptability or versatility
If nodes are connected to both receiving and transmitting circuits simultaneously, then circuit integration is achieved, but equivalent capacitance increases due to superposition of parasitic capacitance
Solution Approach 1:
The patent segments the shared pin functionality into two separate pathways: one through the first T-coil circuit for receiving signals and another through the second T-coil circuit for transmitting signals. This segmentation allows the shared pin to maintain its dual functionality while avoiding the capacitance superposition problem by using separate nodes for each function.
Solution Approach 2:
The patent introduces separate nodes as intermediaries between the shared pin and the receiving/transmitting circuits. The first node serves as an intermediary for the receiving circuit while the second node serves as an intermediary for the transmitting circuit, preventing direct interaction and capacitance superposition between the two circuits.
3Speed
If bandwidth extension circuit is added, then high-frequency response is improved, but circuit complexity increases
Solution Approach 1:
The patent designs the two T-coil circuits to be structurally identical, with each circuit serving its specific function (receiving or transmitting) while following the same design template. This universal approach allows for standardized design and analysis, reducing the cognitive complexity despite the increased number of components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively doubles the basic bandwidth of the transmission line, improving high-frequency response and maintaining good frequency response for low-frequency signals, thus enhancing signal transmission efficiency and quality.
Implementation Method 1
a first inductor, a second inductor... The first inductor is electrically connected between the shared pin and a node. The second inductor is electrically connected to the first inductor through the node.
Implementation Method 2
a first capacitor, a second capacitor and a third capacitor. The first capacitor is electrically connected between the node and a ground. The second capacitor is electrically connected between the shared pin and the ground. The third capacitor is electrically connected between the second inductor and the ground.
Data Source
AI summary
An electronic device includes a shared pin and a bandwidth extension circuit. The electronic device receives or transmits a signal through the shared pin. The bandwidth extension circuit is electrically coupled to the shared pin. The bandwidth extension circuit includes a first inductor, a second inductor, a first capacitor, a second capacitor, and a third capacitor. The first inductor is electrically connected between the shared pin and a node. The second inductor is electrically connected to the first inductor through the node. The first capacitor is electrically connected between the node and a ground. The second capacitor is electrically connected between the shared pin and the ground. The third capacitor is electrically connected between the second inductor and the ground. The first inductor is different from the second inductor. There is no coupling effect between the first inductor and the second inductor.