Shared Data Pin Selection for On-Chip Debug Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of integrated circuits and systems-on-a-chip (SoCs) leads to diminished physical access for testing and debugging, resulting in reduced visibility and control, increased design complexity, and higher costs, making it difficult to detect manufacturing defects and ensure system functionality during the design phase.
Innovation Solution
The integration of on-chip debug facilities with a scalable, modular architecture that allows for dynamic pin sharing and configuration, enabling real-time emulation, data exchange, and advanced analysis capabilities, which can be customized to balance cost and debug needs, and are deployable on a per-pin basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integrated circuits and SoCs are made increasingly complex with denser designs and shrinking interconnect pitch, then system functionality and integration level are improved, but physical access for testing and debugging is diminished
Solution Approach 1:
The patent segments the circuit design by integrating dedicated testability circuitry and emulation interfaces directly into the chip architecture. This segmentation allows test and debug functions to be separated from the main functional logic, providing physical access points without compromising the dense functional integration. The testability features are embedded as distinct modular components within the SoC.
Solution Approach 2:
The patent implements multi-functional interfaces that serve both functional operation and test/debug purposes. The emulation interfaces and testability circuitry are designed to work alongside the main system functions, allowing the same physical infrastructure to support both normal operation and testing activities. This universal approach eliminates the need for separate dedicated test access paths.
2Reliability
If testability circuitry is extensively designed into complex systems, then fault coverage and controllability are improved, but design time and expense increase
Solution Approach 1:
The patent applies design-for-testability principles during the initial logic design phase rather than adding test features later. Testability circuitry is proactively integrated into the architecture from the outset, allowing automatic test equipment to be configured and test patterns to be generated early in the design process. This preliminary action prevents the need for extensive retroactive modifications.
Solution Approach 2:
The patent utilizes configurable parameters and modes that allow the same hardware infrastructure to serve multiple purposes. By changing operational parameters and mode settings, the system can switch between functional operation and test/debug modes, maximizing the utility of the integrated testability features without requiring additional hardware or design iterations.
3Ease of manufacture
If modules are made reusable across multiple applications, then marginal design cost is reduced, but access to the module may be buried in application specific logic
Solution Approach 1:
The patent extracts reusable module interfaces and testability features from application-specific logic by providing dedicated access paths and control mechanisms. The modular components are designed with independent access points that can be controlled without interfering with the surrounding application logic. This extraction allows the same module to be accessed and tested independently across different applications.
Solution Approach 2:
The patent implements a hierarchical nesting structure where reusable modules are embedded within application-specific contexts but maintain independent access interfaces. The modular design allows smaller functional units to be nested within larger system contexts while preserving their individual accessibility through dedicated control and interface pathways, enabling both reusability and independent access.
Data Source
AI summary
This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention plural operational units each having a normal mode and a stall mode controlled by an enable input. Selection logic selectively enables an operation unit and connects the data input/output of the enabled operation unit to the data pin. The operational units are responsive to a preceding or following key to enter the normal mode. Each operational unit switches between stall mode and the normal mode upon receiving a corresponding predetermined selection number of pulses at while the clock input receives a non-cycling signal. Greater number of pulses deselect all operational units, switch operational units to the normal mode if the correct key is received and switch all operational units to the stall mode.