Shared Pin Testing Interface for IC Protocols

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Solution Overview

Problem

Integrated circuit devices require testing with multiple protocols, such as JTAG and SCAN, which increases testing time and necessitates additional input/output pins, making the process inefficient and resource-intensive, especially when dealing with large quantities of devices.

Innovation Solution

An integrated circuit device design that incorporates both JTAG and SCAN protocols using shared input/output pins, allowing for simultaneous or sequential testing without the need for dedicated pins, by determining the protocol based on voltage levels at specific pins, enabling seamless transition between testing protocols.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple dedicated input/output pins are used for different testing protocols, then testing capability and reliability are improved, but device complexity and resource usage increase

Engineering Contradiction:
Improvetesting capabilityVSAvoidnumber of pins
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a universal testing interface where a single set of input/output pins can operate under multiple testing protocols (JTAG and SCAN). The interface includes protocol selection logic that determines which protocol to execute based on control signals, allowing the same physical pins to serve multiple testing functions without requiring dedicated pins for each protocol.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple testing protocols are implemented with dedicated pins, then testing versatility is improved, but manufacturing cost and device resources increase

Engineering Contradiction:
Improvetesting protocol supportVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The testing interface is designed as a universal multi-functional unit that can execute both JTAG and SCAN protocols using the same physical pins. The interface includes protocol identification logic that detects which protocol is being invoked and configures the interface accordingly, eliminating the need for separate dedicated pin sets for each protocol and thereby reducing manufacturing complexity and cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The testing interface dynamically adapts its behavior based on the selected protocol. The interface can switch between JTAG and SCAN protocols during operation, with the ability to enter idle states in one protocol and transition to another protocol as needed. This dynamic adaptability allows a single interface to provide multiple protocol support without requiring static dedicated hardware for each protocol.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If sequential testing with protocol transitions is implemented, then pin usage is reduced, but testing time may increase due to state transitions

Engineering Contradiction:
Improvepin configurationVSAvoidtesting time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The testing interface performs preliminary configuration actions when transitioning between protocols. When a protocol transition is detected, the interface pre-configures the necessary control signals and state machine settings before actually switching protocols. This preliminary preparation minimizes the time required for protocol transitions by having the interface ready to execute the next protocol immediately upon completion of the current one, rather than requiring extensive reconfiguration during the transition.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10162000B2Testing an integrated circuit device with multiple testing protocols
Publication Date: 2018.12.25 NXP BV
  • US10162000B2 patent drawing
  • US10162000B2 patent drawing
  • US10162000B2 patent drawing

AI summary

Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol.