Shared Pipeline ADC Layout for High-Frame-Rate Image Sensors
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Solution Overview
Problem
Current CMOS imaging devices face challenges in achieving high pixel count, high ADC resolution, and high video frame rates due to limitations in analog-to-digital converter architectures, particularly with small pixel sizes less than 3 μm, where conventional column-parallel architectures are inefficient in terms of power consumption and conversion speed.
Innovation Solution
The implementation of a semi-column-parallel pipeline analog-to-digital converter architecture, where multiple column output lines share an analog-to-digital converter, allowing pipelined conversions to reduce row times and increase frame rates, and enabling the use of high-performance, high-resolution converters with improved pitch efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional column-parallel ADC architecture is used, then each column has dedicated ADC converter, but power consumption increases and conversion speed decreases for high pixel count applications
Solution Approach 1:
The pixel array columns are divided into multiple groups, with each group sharing a common ADC converter. This segmentation reduces the total number of ADC converters needed compared to dedicated per-column architecture, thereby reducing power consumption while maintaining conversion speed through parallel processing of multiple column groups
Solution Approach 2:
The system dynamically switches between different column groups for ADC conversion using multiplexers and timing control circuitry. This dynamic switching enables efficient resource utilization where ADC converters are shared across multiple columns temporally, reducing overall power consumption while maintaining high conversion throughput
2Quantity of substance
If pixel size is reduced below 3 μm, then pixel count increases, but conventional ADC architectures become inefficient in power consumption and conversion speed
Solution Approach 1:
Columns are segmented into groups that share ADC converters, enabling the system to handle high pixel counts from small pixels without requiring a proportional increase in ADC converters. This maintains conversion speed efficiency even as pixel count increases
Solution Approach 2:
ADC converters are designed to serve multiple column groups universally through time-multiplexed operation. Each ADC converter can process signals from different column groups at different time intervals, enabling high pixel count support without sacrificing conversion speed
3Measurement precision
If dedicated ADC converter is assigned to each column, then conversion resolution can be maintained, but device area and complexity increase
Solution Approach 1:
The system segments columns into groups that share ADC converters, reducing the total number of ADC converters and associated control logic. This segmentation maintains measurement precision through proper signal routing and timing while significantly reducing device complexity
Solution Approach 2:
Multiplexers and buffer circuits act as intermediaries between column groups and shared ADC converters. These intermediary components enable multiple columns to access the same ADC resource without compromising signal integrity or conversion precision, while reducing overall system complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in shorter row times, higher frame rates, and increased data throughput, overcoming the shortcomings of serial and column-parallel architectures, enabling CMOS imaging devices to handle high pixel counts, high resolutions, and high frame rates effectively.
Implementation Method 1
a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge
Data Source
AI summary
An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined manner to reduce the conversion time, which results in shorter row times and increased frames rate and data throughput. The architecture also enhances the pitch of the analog-to-digital converters, which allows high performance, high resolution analog-to-digital converters to be used. As such, semi-column-parallel pipeline architecture overcomes the shortcomings of the typical serial and column-parallel architectures.