Shared Pixel Circuits for Ultra-High-Resolution Displays

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Solution Overview

Problem

Conventional display apparatuses face limitations in integration due to the high number of transistors and capacitors in each sub-pixel, preventing their application in ultra-resolution displays.

Innovation Solution

The display apparatus incorporates a pixel design where sub-pixels share functional circuits, reducing the number of transistors and capacitors by utilizing pulse width and amplitude modulators, initializers, voltage drop compensators, and light emitting element initializers, allowing for improved integration and compatibility with ultra-high resolution displays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If each sub-pixel includes multiple transistors and capacitors for pulse width modulation and amplitude modulation, then the display quality and control precision are improved, but the integration density and pixel area are reduced

Engineering Contradiction:
Improvedisplay qualityVSAvoidpixel area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent combines the initialization functions for both sub-pixels into a single initializer circuit that responds to a second initialization signal. This merging of initialization circuits reduces the total number of transistors and capacitors required in each pixel, thereby improving integration density while maintaining the necessary display quality through shared functional circuits.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements shared functional circuits including a common voltage drop compensator, initializer, and light emitting element initializer that serve multiple sub-pixels. These universal circuits perform multiple functions across different sub-pixels, reducing overall circuit complexity and pixel area while preserving precise control capabilities through the pulse width and amplitude modulators.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If the number of transistors and capacitors in each sub-pixel is reduced through sharing functional circuits, then the integration density is improved, but the circuit complexity for maintaining display quality may increase

Engineering Contradiction:
Improveintegration densityVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the display into multiple sub-pixels within a pixel, where each sub-pixel has dedicated pulse width and amplitude modulators for precise control. Meanwhile, common functions like initialization and voltage compensation are shared across sub-pixels. This segmentation strategy reduces overall circuit complexity by eliminating redundant circuits while maintaining high integration density through efficient resource allocation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12444366B2Display apparatus
Publication Date: 2025.10.14 SAMSUNG DISPLAY CO LTD
  • US12444366B2 patent drawing
  • US12444366B2 patent drawing
  • US12444366B2 patent drawing

AI summary

A display apparatus includes a pixel including a first sub-pixel including a first pulse width modulator outputting a first gate output signal for pulse width modulation in response to a first pulse width data and controlling a first driving current of a first light emitting element and a first pulse amplitude modulator applying the first driving current to the first light emitting element in response to a first pulse amplitude data, a second sub-pixel including a second pulse width modulator outputting a second gate output signal for pulse width modulation in response to a second pulse width data and controlling a second driving current of a second light emitting element and a second pulse amplitude modulator applying the second driving current to the second light emitting element in response to a second pulse amplitude data and an initializer initializing the first gate output signal and the second gate output signal.