Image Sensor Shared Pixel Architecture Reducing Digital Line Memory

The pixel array is divided into multiple banks, and the readout circuit is segmented into multiple corresponding readout circuits. Each readout circuit handles a specific bank, allowing parallel processing of pixel signals from different banks. This segmentation reduces the need for large digital line memories by enabling simultaneous readout operations across multiple channels, thereby reducing overall device size while managing complexity through modular architecture.

The patent introduces a bank dimension to the traditional row-column pixel array structure. By organizing pixels into multiple banks that can be independently controlled and read out, the system adds a spatial dimension to the readout process. This allows multiple rows from different banks to be read out simultaneously, reducing the temporal requirement for large memory buffers and thus reducing device size.

The patent combines multiple readout operations into parallel channels by dividing the pixel array into banks. Instead of using a single large memory to store all pixel signals sequentially, multiple smaller readout circuits process signals from different banks simultaneously. This merging of parallel processing paths improves signal processing efficiency while reducing the total memory capacity required, as each channel handles a subset of the data.

The row control portion controls multiple sequential rows simultaneously to output pixel signals through different banks in parallel. This preliminary organization of rows into controllable groups allows the readout circuit to process multiple rows of pixel signals concurrently, improving processing efficiency without requiring large memory buffers to hold all signals before processing.

The pixel array is segmented into multiple banks with different readout paths. By routing pixel signals from different banks through separate readout circuits, the patent prevents color noise from accumulating along a single readout path. Simultaneous readout of multiple rows is achieved by distributing them across different banks, maintaining readout speed while eliminating the color noise problem that would occur in a single-path architecture.

The bank structure acts as an intermediary between the pixel array and the readout circuit. Instead of directly reading out all rows through a single path, the bank structure mediates the signal flow by distributing rows to different readout circuits. This intermediary organization enables parallel readout while preventing color noise accumulation, as each bank's signals are processed independently before being combined at a later stage.