Shared-Transistor Pixel Layout for Faster Image Sensor Readout
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Solution Overview
Problem
Existing image sensors face challenges in optimizing the arrangement and sharing of transistors within the pixel area to enhance signal transfer speed and reduce dark current or noise, particularly due to the limitations of transistor area configuration and isolation methods.
Innovation Solution
The image sensor design includes a transistor set with a specific arrangement of reset, source follower, and selection transistors, where transistors share common source or drain areas, and the transistors are connected in parallel to increase channel width, thereby improving transconductance and reducing RC delay, while eliminating the need for separate isolation areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are arranged in a conventional layout, then the photodiode area is reduced, but the signal transfer speed and transconductance are insufficient
Solution Approach 1:
Adjacent transistors share common source or drain areas, merging previously separate regions into shared structures. This reduces the total transistor area while maintaining electrical functionality, thereby increasing the photodiode area without compromising signal transfer speed
Solution Approach 2:
The transistor layout transitions from a conventional planar arrangement to a shared-area configuration where source and drain regions serve multiple transistors simultaneously. This dimensional reorganization optimizes space utilization and improves signal transfer characteristics
2Area of stationary object
If transistors are arranged to increase photodiode area, then the transistor area is reduced, but RC delay increases
Solution Approach 1:
By merging source and drain areas between adjacent transistors, the patent reduces the total number of discrete regions, thereby decreasing overall capacitance and resistance products. This shared-area architecture reduces RC delay while accommodating smaller transistor footprints
3Speed
If conventional transistor layout is used, then signal transfer speed is limited, but dark current and noise are not optimized
Solution Approach 1:
The shared source and drain areas between adjacent transistors create a more compact and electrically efficient structure. This merging reduces parasitic effects and optimizes charge transfer, thereby increasing signal transfer speed while minimizing dark current and noise generation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances signal transfer speed and reduces dark current or noise by improving transconductance and minimizing RC delay, while also eliminating the need for separate isolation areas, thus improving overall image sensor performance.
Implementation Method 1
The pixel area may include a photodiode
Data Source
AI summary
An image sensor for securing an area of a photodiode includes a pixel area and a transistor area adjacent to the pixel area. The pixel area may include a photodiode and a floating diffusion area. The transistor area may include transistors extending along an edge of the pixel area. The transistors in the transistor area may include a reset transistor, one or more source follower transistors, and one or more selection transistors, and the reset transistor and one source follower transistor adjacent to the reset transistor may share a common drain area. The source follower transistors and the selection transistors may each share a common source area or a common drain area between two adjacent transistors thereof.