Shared Pixel Storage Gate Architecture for CMOS Imager Fill Factor
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Solution Overview
Problem
Conventional CMOS imager designs have a low fill factor, which limits the sensitivity and efficiency of pixel cells, as only half of the pixel area is utilized for photosensitive components, and the addition of storage or anti-blooming transistors further decreases the photosensor fill factor.
Innovation Solution
A shared pixel cell architecture where multiple pixels share common components such as storage gates, anti-blooming gates, and readout circuits, increasing the fill factor and quantum efficiency by optimizing the layout to maximize photosensitive area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS imager designs with individual storage transistors per pixel are used, then charge storage and readout functionality is achieved, but the photosensor fill factor decreases to approximately 50%
Solution Approach 1:
Multiple pixel cells share common storage gates and readout circuitry. Specifically, four pixel cells share a single storage gate (SG) and associated readout transistor, eliminating the need for individual storage transistors in each pixel. This merging of components significantly increases the photosensor fill factor while maintaining charge storage and readout functionality through the shared infrastructure.
2Reliability
If storage transistors and anti-blooming transistors are added to increase charge capacity and prevent overflow, then pixel functionality is enhanced, but the photosensitive area is further reduced
Solution Approach 1:
The shared storage gate serves multiple functions: it acts as a storage gate for photocharge accumulation, an anti-blooming gate to prevent charge overflow, and a transfer gate to move charge to the readout circuit. This multi-functionality eliminates the need for separate dedicated transistors for each function, thereby preserving photosensitive area while maintaining enhanced charge capacity and anti-blooming protection.
3Productivity
If pixel area is reduced for scaling, then device density increases, but sensitivity decreases due to smaller photosensor area
Solution Approach 1:
By merging storage and readout components across multiple pixels, the photosensor area within each pixel can be maximized. The shared storage gate and readout circuitry are positioned in the inter-pixel regions, allowing individual pixel sensors to occupy nearly the entire pixel area, thereby maintaining high sensitivity even as overall device density increases through scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shared component architecture enhances the fill factor and quantum efficiency of the pixel array, allowing for more efficient light conversion and charge handling while minimizing non-photosensitive area, thereby improving the overall performance of the CMOS imager.
Implementation Method 1
When incident light 187 strikes the surface of a photosensor (photodiode) 120, electron/hole pairs are generated in the p-n junction of the photosensor
Data Source
AI summary
A pixel array includes a first photosensor for generating charge in response to applied light, a second photosensor for generating charge in response to applied light, and a first and second storage transistor having a common first storage gate respectively connected to said first and second photosensors for storing charge from said first and second photosensors in respective first and second storage regions.