Shared Plate Planar Capacitors for Dense Memory Integration
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Solution Overview
Problem
Integrating capacitors, including ferroelectric or paraelectric materials, on the same plane as interconnects of logic devices is challenging due to spacing issues and difficulties in connecting transistors and routing interconnects, limiting charge storage and device operation.
Innovation Solution
A shared plate electrode structure is used to couple multiple capacitors to a single transistor, with flexible shape and size adjustments, and a dual hydrogen barrier to protect against hydrogen diffusion, ensuring efficient integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are integrated on the same plane as interconnects of logic devices, then charge storage capability is improved, but spacing between capacitors becomes constrained and routing interconnects becomes difficult
Solution Approach 1:
The patent transitions from planar capacitor integration to three-dimensional vertical stacking. Multiple capacitor layers are stacked above the substrate, with shared plate electrodes extending vertically to connect multiple capacitor layers. This dimensional change allows increased charge storage capacity without constraining the horizontal spacing between capacitors, as capacitors are arranged in the vertical dimension rather than competing for planar space.
2Productivity
If capacitor spacing is scaled down to increase density, then device integration density is improved, but connections between transistors and routing interconnects become challenging
Solution Approach 1:
The patent merges multiple capacitor structures by implementing shared plate electrodes that are commonly shared among multiple capacitors. The plate electrode structure extends vertically to serve as a common connection point for multiple capacitors, reducing the number of separate interconnect routes needed. This merging approach maintains high integration density while simplifying the connection network between transistors and capacitors.
Solution Approach 2:
By moving to vertical stacking with plate electrodes extending in the vertical dimension, the patent reduces horizontal routing complexity. The shared plate electrodes provide vertical access to multiple capacitors, eliminating the need for complex horizontal interconnect routing that would be required to connect closely-spaced planar capacitors to transistors.
3Quantity of substance
If multiple capacitors are coupled to increase charge storage, then memory capacity is improved, but the number of interconnects and transistors required increases device complexity
Solution Approach 1:
The patent combines multiple capacitors into a unified vertical stack that shares common plate electrodes and can be controlled by shared transistor connections. This merging allows multiple capacitors to function as an integrated memory unit, increasing memory capacity without proportionally increasing the number of transistors and interconnects required, as the shared structure reduces redundant connection elements.
Data Source
AI summary
A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.