Shared Plate Trench Capacitors for Dense Ferroelectric Memory Integration
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Solution Overview
Problem
The integration of capacitors, particularly ferroelectric or paraelectric ones, on the same plane as interconnects of logic devices is challenging, especially when scaling down, due to difficulties in connecting transistors and routing interconnects.
Innovation Solution
A device structure that couples multiple memory devices using a shared plate electrode, which is positioned within the vicinity of the capacitors, allowing for flexible arrangement and connection of capacitors to a single transistor, while also incorporating electrode structures and hydrogen barriers to prevent hydrogen diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are integrated on the same plane as interconnects of logic devices, then charge storage capacity is improved, but manufacturing complexity and routing difficulty increase
Solution Approach 1:
The patent transitions from planar capacitor integration to three-dimensional trench capacitor structures. By etching trenches into the substrate and forming capacitors vertically within these trenches, the design moves from two-dimensional plane integration to three-dimensional spatial utilization. This allows multiple capacitors to be stacked and integrated without occupying additional planar space, thereby increasing charge storage capacity while managing integration complexity through vertical rather than lateral expansion.
Solution Approach 2:
The patent implements nested structures where trench capacitors are formed within trenches that are etched into the substrate. The capacitor structures are nested within the trench boundaries, and multiple trenches can be arranged in arrays. This nesting approach allows compact integration of multiple capacitors in a confined space, improving charge storage capacity while maintaining controlled manufacturing complexity through standardized trench formation processes.
2Area of moving object
If spacing between capacitors is scaled down, then device density is improved, but connection and routing between transistors and capacitors becomes more difficult
Solution Approach 1:
By forming capacitors in vertical trench structures rather than planar configurations, the patent reduces the planar footprint required per capacitor. This vertical integration allows capacitors to be packed more densely in the lateral direction without increasing the complexity of interconnect routing, as the trench structures provide well-defined access points for connections at the trench openings.
Solution Approach 2:
The patent divides the capacitor structure into segmented components: the trench region, the capacitor dielectric, the top and bottom electrodes, and the surrounding isolation material. This segmentation allows each component to be optimized independently and facilitates modular manufacturing processes, making it easier to manufacture high-density capacitor arrays with precise spacing and connections.
3Quantity of substance
If trench capacitors are formed with precise spacing, then charge storage efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary actions in the form of sacrificial layers and mandrels that are deposited and patterned before the actual trench capacitor formation. These preliminary structures serve as templates that define the trench locations and spacing, ensuring precise positioning is achieved through self-aligned processes rather than direct patterning of the final capacitor structures.
Solution Approach 2:
The patent uses intermediary materials such as sacrificial layers, spacer materials, and mandrels that mediate the formation of the trench capacitors. These intermediary structures enable precise spacing control through controlled deposition thicknesses and self-aligned etching processes, reducing the direct manufacturing precision requirements on the final capacitor dimensions while still achieving the desired spacing and charge storage efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances charge storage capacity and facilitates the operation of memory and logic devices by allowing for efficient coupling of multiple capacitors, while also protecting the devices from hydrogen diffusion, which can damage the ferroelectric material.
Implementation Method 1
incorporating electrode structures and hydrogen barriers to prevent hydrogen diffusion
Data Source
AI summary
A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.