Shared PLL Audio Clock Recovery Without a Second PLL
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Solution Overview
Problem
The existing HDMI interface technologies require a second PLL for audio clock recovery, which consumes significant power and area, increasing the cost and complexity of integrated circuits.
Innovation Solution
A shared-PLL approach is used to recover an audio clock without a second PLL, employing a programmable divider to generate a playback clock from a synchronized reference clock, allowing for flexible clock rate multiples to optimize audio data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second PLL is used for audio clock recovery, then audio clock recovery is achieved, but power consumption and area requirements increase
Solution Approach 1:
The patent combines the video data recovery function and audio clock recovery function into a single PLL circuit. The PLL simultaneously performs both functions by using the same phase-locked loop mechanism for both video data reconstruction and audio clock generation, thereby eliminating the need for a second dedicated PLL and reducing overall power consumption.
Solution Approach 2:
The single PLL is designed to perform multiple functions: it recovers video data from the TMDS signal and generates the audio master clock (MCLK) for audio playback. This multi-functional approach allows one circuit to replace what would traditionally require two separate circuits, reducing area and power while maintaining reliability.
2Reliability
If a second PLL is used for audio clock recovery, then audio clock recovery is achieved, but area requirements and circuit complexity increase
Solution Approach 1:
The patent merges the video data recovery path and audio clock recovery path into a single shared PLL structure. By combining these functions in one circuit block rather than using two separate PLLs, the substrate area required is significantly reduced while still achieving reliable audio clock recovery.
Solution Approach 2:
The single PLL is designed to be universal, handling both video data reconstruction and audio clock generation. This multi-functionality reduces the total circuit area by eliminating redundant components that would be present in a traditional dual-PLL architecture.
3Reliability
If traditional PLLs are used, then clock recovery is achieved, but special layout and electrical requirements increase cost
Solution Approach 1:
By combining video data recovery and audio clock recovery into a single PLL, the patent reduces the number of high-speed signal paths and sensitive electrical connections required. This simplification eases layout constraints and reduces the specialized manufacturing requirements that would otherwise increase circuit cost.
Data Source
AI summary
A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.