Shared PLL RF Integrated Circuit for Carrier Aggregation

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Solution Overview

Problem

Current RF integrated circuits face challenges in reducing design area and efficiently consuming power during communication operations, particularly due to the need for multiple local oscillators for carrier aggregation, which increases size and power consumption.

Innovation Solution

The RF integrated circuit employs a shared phase locked loop circuit to provide frequency signals to multiple receiving and transmitting circuits, eliminating the need for individual local oscillators and enabling efficient frequency conversion through analog to digital and digital to analog conversions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple local oscillators are used for carrier aggregation, then carrier aggregation capability is supported, but design area and power consumption increase

Engineering Contradiction:

Improvecarrier aggregation capabilityVSAvoiddesign area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple local oscillator functions into a single shared phase locked loop circuit. The PLL circuit generates a master clock signal that is distributed to multiple receiving circuits, eliminating the need for separate local oscillators in each receiving circuit. This combining approach reduces the overall design area while maintaining carrier aggregation capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared phase locked loop circuit is designed to serve multiple receiving circuits simultaneously. By making the PLL circuit universal and capable of supporting multiple carriers through frequency division and signal distribution, the patent achieves carrier aggregation functionality without requiring dedicated local oscillators for each carrier, thus reducing design area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple local oscillators are used for carrier aggregation, then carrier aggregation capability is supported, but power consumption increases

Engineering Contradiction:

Improvecarrier aggregation capabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent combines multiple local oscillator functions into a single shared phase locked loop circuit. By having one PLL circuit serve multiple receiving circuits through clock distribution and frequency synthesis, the total power consumption is reduced compared to running multiple independent local oscillators, while still supporting carrier aggregation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared PLL circuit is designed with universal functionality to support multiple carriers and receiving circuits. Through efficient frequency division and signal distribution mechanisms, it provides the necessary clock signals for carrier aggregation across multiple receivers, minimizing power consumption by avoiding redundant oscillator circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If a shared phase locked loop circuit is used, then design area is reduced, but frequency signal distribution complexity increases

Engineering Contradiction:

Improvedesign areaVSAvoidfrequency signal distribution complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary clock distribution mechanism within the shared PLL circuit. This intermediary structure efficiently manages the distribution of master clock signals to multiple receiving circuits through controlled signal routing and frequency division, reducing the apparent complexity at the system level while maintaining compact design.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Adaptability or versatility

If analog to digital conversion is performed in multiple receiving circuits, then carrier aggregation is supported, but power consumption and design area increase

Engineering Contradiction:

Improvecarrier aggregation supportVSAvoiddesign complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the frequency synthesis and signal distribution functions into a shared PLL circuit that serves all receiving circuits. By centralizing the oscillation and frequency management functions, the patent reduces the overall device complexity while maintaining the ability to support multiple carriers and ADC operations in parallel receiving circuits.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10951445B2Radio frequency integrated circuit supporting carrier aggregation and wireless communication device including the same

Publication Date: 2021.03.16 SAMSUNG ELECTRONICS CO LTD

AI summary

A radio frequency (RF) integrated circuit is provided. The RF integrated circuit supports carrier aggregation and includes first receiving circuits and a first shared phase locked loop circuit that provides a first frequency signal of a first frequency to the first receiving circuits. One of the first receiving circuits includes an analog to digital converter (ADC) and a digital conversion circuit. The ADC converts an RF signal received by the one of the first receiving circuits to a digital signal by using the first frequency signal. The digital conversion circuit generates a digital baseband signal by performing frequency down conversion on the digital signal.