Shared PLL Clock Calibration for Two-Chip Die Skew Alignment
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Solution Overview
Problem
In two-chip die modules, clock skew occurs due to variations in chip processing, power supply setpoints, and package signal propagation asymmetries, leading to compromised latch setup and hold timing margins, necessitating a method to calibrate arrival times of launch and capture clocks to minimize chip-to-chip timing effects.
Innovation Solution
A two-chip die module with a single phase lock loop (PLL) providing a common clock signal, employing programmable delay units and skew adjust/phase detect units to equalize clock signal travel distances and minimize delay differences, along with built-in self-test engines for error checking and data pattern generation to quantify and null out clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate PLLs are used in each chip, then each chip can operate independently, but clock skew between chips increases
Solution Approach 1:
The patent merges the clock generation function by using a single PLL located on one chip to provide clock signals to both chips in the module. This consolidation eliminates inter-PLL skew while maintaining independent chip operation through the distributed clock distribution network that delivers synchronized clock signals to both chips.
2Ease of operation
If clock signals are distributed over asymmetric package interconnects, then chip-to-chip communication is enabled, but clock skew increases due to unequal signal propagation distances
Solution Approach 1:
The patent intentionally introduces asymmetric programmable delay elements into the clock distribution path to compensate for the inherent asymmetry in package interconnect lengths. By measuring the actual skew and programming appropriate delay values, the system creates artificial asymmetry that counterbalances the physical interconnect asymmetry, achieving symmetric clock arrival times at both chips.
Solution Approach 2:
The patent dynamically adjusts the delay parameters of programmable delay elements in the clock distribution network. By changing the delay parameter values based on measured skew conditions, the system optimizes clock arrival times to minimize skew, transforming fixed timing characteristics into adjustable parameters that adapt to actual signal propagation conditions.
3Device complexity
If fixed clock distribution is used, then system complexity is reduced, but timing margins are compromised due to process variations and power supply differences
Solution Approach 1:
The patent transforms the static, fixed clock distribution system into a dynamic one with programmable delay elements that can be adjusted based on actual operating conditions. This dynamic capability allows the system to adapt to process variations and power supply differences by optimizing delay values, thereby maintaining adequate timing margins without requiring excessive design conservatism.
Solution Approach 2:
The patent implements a feedback mechanism where clock skew is measured and used to program appropriate delay values in the distributed PLL. This closed-loop approach continuously optimizes timing margins by adjusting delay parameters based on actual signal propagation characteristics, ensuring reliable latch setup and hold timing despite variations in operating conditions.
4Reliability
If multiple PLLs are used for redundancy, then system reliability improves, but clock skew and synchronization difficulty increase
Solution Approach 1:
The patent consolidates the PLL function into a single shared resource that serves both chips, eliminating inter-PLL skew entirely. This single PLL provides redundant clock signals to both chips through the distributed clock network, maintaining reliability while avoiding the synchronization problems inherent in multiple independent PLLs.
Data Source
AI summary
A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.