Multi-Channel Clock Circuit with Shared PLL and Local Dividers
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Solution Overview
Problem
Integrated circuits face challenges in balancing individual communication channel capability with resource sharing among multiple channels, particularly in high-speed serial communication protocols where synchronization and independence are required.
Innovation Solution
The implementation of a shared clock management unit (CMU) circuitry with phase-locked loops (PLL) and global and local frequency divider circuitry allows transmitter channels to use either globally generated or locally generated clock signals, enabling synchronization among channels while allowing for independent operation, thus optimizing resource sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLL circuits are provided for each transmitter channel to enable independent operation, then individual channel capability is improved, but device complexity, noise, space, and power consumption increase
Solution Approach 1:
Multiple transmitter channels share a single common PLL circuit instead of each channel having its own dedicated PLL. This merging approach reduces the total number of PLL circuits, thereby decreasing device complexity, noise, space, and power consumption while maintaining the ability of each channel to operate independently through individual frequency divider circuitry.
Solution Approach 2:
The clock management function is segmented into two independent parts: a shared common PLL circuit that generates the base clock signal, and individual frequency divider circuits in each transmitter channel that independently divide the clock signal to different frequencies. This segmentation allows channels to share resources while maintaining independent operation capability.
2Adaptability or versatility
If multiple PLL circuits are provided for each transmitter channel to support different communication protocols, then protocol versatility is improved, but power consumption increases
Solution Approach 1:
Multiple transmitter channels share a single common PLL circuit instead of each channel having its own dedicated PLL. This merging approach reduces the total number of PLL circuits, thereby decreasing device complexity, noise, space, and power consumption while maintaining the ability of each channel to operate independently through individual frequency divider circuitry.
Solution Approach 2:
The common PLL circuit serves multiple transmitter channels simultaneously, providing a universal clock source that can support different communication protocols. Each channel's frequency divider circuitry can independently configure the clock frequency to match different protocol requirements, making the system multi-functional without requiring separate PLL circuits for each protocol.
3Adaptability or versatility
If multiple PLL circuits are provided for each transmitter channel to ensure independent operation, then channel independence is improved, but area occupied by circuitry increases
Solution Approach 1:
Multiple transmitter channels share a single common PLL circuit instead of each channel having its own dedicated PLL. This merging approach reduces the total number of PLL circuits, thereby decreasing device complexity, noise, space, and power consumption while maintaining the ability of each channel to operate independently through individual frequency divider circuitry.
Solution Approach 2:
The clock management function is segmented into two independent parts: a shared common PLL circuit that generates the base clock signal, and individual frequency divider circuits in each transmitter channel that independently divide the clock signal to different frequencies. This segmentation allows channels to share resources while maintaining independent operation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for multiple PLL circuits, minimizing noise, space, and power consumption while enabling flexible protocol support by allowing channels to operate either synchronously or independently, depending on the communication protocol requirements.
Implementation Method 1
The CMU circuitry includes at least one phase-locked loop ('PLL') circuit for producing a primary clock signal
Implementation Method 2
global frequency divider circuitry for producing one or more secondary clock signals from the primary clock signal
Data Source
AI summary
A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.