Shared PLL Loop Filter for 3D Die Area Reduction
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Solution Overview
Problem
Existing three-dimensional integrated circuits (3DICs) face challenges with large PLLs occupying significant die area, leading to increased total die area and reduced functional capacity per volume unit due to each die requiring an individual clock generation system.
Innovation Solution
Implementing a shared loop filter among PLLs in a die stack, where the clock phase of each PLL takes turns locking with a reference clock, utilizing a programmable connection element and capacitors to adaptively control the loop filter's bandwidth, allowing multiple dies to share the same loop filter and reduce die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each die in a die stack includes an individual PLL to generate clocks at different frequencies, then each die can operate independently with its own clock, but the total die area increases significantly
Solution Approach 1:
Multiple PLLs across different dies share a common loop filter and frequency divider resources. The loop filter is physically implemented once and electrically connected to multiple VCOs through selective routing, allowing simultaneous operation of multiple PLLs with reduced total area compared to fully independent implementations.
Solution Approach 2:
The shared loop filter and frequency divider are designed to serve multiple PLLs simultaneously. The frequency divider can divide frequencies for multiple VCOs, and the loop filter processes feedback from multiple PLL loops, making these components universal resources that reduce redundancy in the clock generation system.
2Adaptability or versatility
If each die includes a complete PLL system, then each die has full clock generation capability, but the functional capacity per volume unit decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture. PLLs are distributed across multiple vertical layers (dies), allowing shared resources to be implemented in the vertical dimension while maintaining independent clock generation capabilities across different functional blocks.
Solution Approach 2:
The PLL system is segmented into functional modules distributed across multiple dies. Critical shared resources (loop filter, frequency divider) are implemented once and shared, while VCOs and other die-specific components are distributed across individual dies, optimizing the balance between shared and dedicated functionality.
3Area of stationary object
If PLLs share a common loop filter, then die area is reduced, but the clock phase locking process becomes more complex
Solution Approach 1:
The shared loop filter is selectively connected to different PLLs in a periodic or time-multiplexed manner. Each PLL takes turns using the shared loop filter resource, with control logic that switches the connection based on which PLL needs phase locking at any given moment, reducing area while managing complexity through temporal separation.
Data Source
AI summary
A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL.