Shared Digital PLL Timing Recovery for Multiplexed Packet Streams
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Solution Overview
Problem
The variation in packet transmission time between digital source and sink devices, especially when packet streams are multiplexed, makes it difficult for the sink device to synchronize with the source clock frequency, leading to issues like improper decoding or loss of picture.
Innovation Solution
A system comprising a memory, digital phase-locked loop (PLL), error calculation unit, output timestamp generator, and control unit that calculates and adjusts the source frequency estimate using low-pass digital filters and timestamp data to minimize clock frequency variation, ensuring accurate synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet streams are multiplexed onto the same channel, then channel utilization is improved, but packet transmission time variation increases
Solution Approach 1:
The system pre-calculates expected timestamps and source frequency estimates for each packet stream before actual transmission. By maintaining a memory of anticipated timing parameters for multiple streams, the system prepares synchronization data in advance, allowing the sink device to compensate for multiplexing-induced delays without real-time adjustments.
Solution Approach 2:
The digital phase-locked loop continuously monitors actual packet arrival times and compares them against expected timestamps. The error calculation unit computes frequency estimates based on this feedback, and the system adjusts timing parameters dynamically to compensate for variations introduced by multiplexing, maintaining synchronization despite channel sharing.
2Adaptability or versatility
If transmission time varies between packets, then multiplexing flexibility is improved, but clock frequency synchronization becomes difficult
Solution Approach 1:
The system changes the timestamp parameter dynamically based on measured transmission variations. By calculating expected timestamps that account for multiplexing delays and adjusting source frequency estimates in real-time, the system maintains accurate clock synchronization even as transmission conditions change due to multiplexing operations.
3Device complexity
If a single PLL is shared across multiple streams, then device complexity is reduced, but measurement precision for each stream decreases
Solution Approach 1:
The system segments the handling of multiple packet streams by maintaining separate expected timestamp and source frequency estimate data in memory for each stream. Although a single digital PLL is used, it processes each stream's timing parameters independently through sequential read operations, preserving measurement precision for each individual stream while sharing the hardware resource.
Data Source
AI summary
A system including a memory (storing a set of data records), a digital phase-locked loop (PLL) and digital circuitry. Each of the data records is allocated to one packet stream in a set of packet streams. The digital circuitry is configured to: invoke a read operation from the memory in response to a received stream indicator and received channel indicator corresponding to a current timestamp-bearing packet; generate an output timestamp for the current packet equal to an expected timestamp provided by the memory as part of the read operation; and generate error data based on argument data including a received input timestamp, a received slot delay value, a previous source frequency estimate and an expected timestamp provided as part of the read operation. The digital PLL is configured to compute an updated source frequency estimate based on information including the error data and the previous source frequency estimate.